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  1. # Release Notes
  2. ### 2.6 [2020-02-23]
  3. - support VHDL-2008 block comment /* */
  4. - use jest
  5. - indent multi-line signal and constant declarations
  6. - do not add space between "<" or ">"; e.g. "<<<" will become " <<< " and not " < < < "
  7. - array type definition breaks when formatting; e.g. "RANGE <>" becomes "RANGE < >"
  8. ### 2.5 [2019-03-13]
  9. - keep the front page concise
  10. - add `style.css`, improve UI
  11. - support all browsers (do not use `RegExp Lookbehind Assertions`)
  12. ### 2.4 [2019-02-23]
  13. - use local storage to store settings
  14. - add `main.js`
  15. - treat key words and type names separately
  16. - expand/hide setting options
  17. - align signs locally or globally
  18. ### 2.3 [2019-02-22]
  19. - bugfix "remove non-comment code by mistake"
  20. - add `tests` folder, improve the project management
  21. - support extended identifier (backslash names)
  22. - fix exponential notation
  23. - user can choose EOL symbols (or use system's by default)
  24. - align comments (when user chooses "align" option)
  25. - bugfix "extra whitespaces around unary minus or plus"
  26. Many thanks to [@MihaiBabiac](https://github.com/MihaiBabiac)
  27. ### 2.2 [2018-10-16]
  28. - support enumerated types
  29. ### 2.1 [2018-03-22]
  30. - fix keywords case issues
  31. - anything in quotes will not be touched
  32. - correct format for comments after multi-line statement
  33. - options to align signs in parameter lists
  34. - fix function indentation
  35. - fix "align symbols affects process label"
  36. - do not align multi-occurrence symbols in a line
  37. - better styles (checkbox, button, disabled)
  38. - support package bodies
  39. - fix "newline after PORT affects PORT MAP"
  40. ### 2.0 [2018-02-16]
  41. - rewrite the main algorithm (& move to a new repository)
  42. - add more unit tests
  43. - fix all known issues
  44. ### 1.1 [2016-11]
  45. - fix some bugs reported by users
  46. - add unit tests
  47. ### 1.0 [2015-01]
  48. - support most of the VHDL features