align in, out, buffer and inout key words

VHDLFormatter.js

@@ -492,9 +492,21 @@ function AlignSigns(result, startIndex, endIndex, mode) {
     AlignSign_(result, startIndex, endIndex, ":=", mode);
     AlignSign_(result, startIndex, endIndex, "<=", mode);
     AlignSign_(result, startIndex, endIndex, "=>", mode);
+    AlignSign_(result, startIndex, endIndex, "direction", mode);
     AlignSign_(result, startIndex, endIndex, "@@comments", mode);
 }
 exports.AlignSigns = AlignSigns;
+function indexOfGroup(regex, input, group) {
+    var match = regex.exec(input);
+    if (match == null) {
+        return -1;
+    }
+    var index = match.index;
+    for (let i = 1; i < group; i++) {
+        index += match[i].length;
+    }
+    return index;
+}
 function AlignSign_(result, startIndex, endIndex, symbol, mode) {
     let maxSymbolIndex = -1;
     let symbolIndices = {};
@@ -512,11 +524,23 @@ function AlignSign_(result, startIndex, endIndex, symbol, mode) {
         if (symbol == ":" && line.regexStartsWith(labelAndKeywordsRegex)) {
             continue;
         }
-        let regex = new RegExp("([\\s\\w\\\\]|^)" + symbol + "([\\s\\w\\\\]|$)");
+        let regex;
+        if (symbol == "direction") {
+            regex = new RegExp("(:\\s*)(IN|OUT|INOUT|BUFFER)(\\s+)(\\w)");
+        }
+        else {
+            regex = new RegExp("([\\s\\w\\\\]|^)" + symbol + "([\\s\\w\\\\]|$)");
+        }
         if (line.regexCount(regex) > 1) {
             continue;
         }
-        let colonIndex = line.regexIndexOf(regex);
+        let colonIndex;
+        if (symbol == "direction") {
+            colonIndex = indexOfGroup(regex, line, 4);
+        }
+        else {
+            colonIndex = line.regexIndexOf(regex);
+        }
         if (colonIndex > 0) {
             maxSymbolIndex = Math.max(maxSymbolIndex, colonIndex);
             symbolIndices[i] = colonIndex;

VHDLFormatter.ts

@@ -554,9 +554,22 @@ export function AlignSigns(result: (FormattedLine | FormattedLine[])[], startInd
     AlignSign_(result, startIndex, endIndex, ":=", mode);
     AlignSign_(result, startIndex, endIndex, "<=", mode);
     AlignSign_(result, startIndex, endIndex, "=>", mode);
+    AlignSign_(result, startIndex, endIndex, "direction", mode);
     AlignSign_(result, startIndex, endIndex, "@@comments", mode);
 }
 
+function indexOfGroup(regex: RegExp, input: string, group: number) {
+    var match = regex.exec(input);
+    if (match == null) {
+        return -1;
+    }
+    var index = match.index;
+    for (let i = 1; i < group; i++) {
+        index += match[i].length;
+    }
+    return index;
+}
+
 function AlignSign_(result: (FormattedLine | FormattedLine[])[], startIndex: number, endIndex: number, symbol: string, mode: string) {
     let maxSymbolIndex: number = -1;
     let symbolIndices = {};
@@ -574,12 +587,23 @@ function AlignSign_(result: (FormattedLine | FormattedLine[])[], startIndex: num
         if (symbol == ":" && line.regexStartsWith(labelAndKeywordsRegex)) {
             continue;
         }
-
-        let regex: RegExp = new RegExp("([\\s\\w\\\\]|^)" + symbol + "([\\s\\w\\\\]|$)");
+        let regex: RegExp;
+        if (symbol == "direction") {
+            regex = new RegExp("(:\\s*)(IN|OUT|INOUT|BUFFER)(\\s+)(\\w)");
+        }
+        else {
+            regex = new RegExp("([\\s\\w\\\\]|^)" + symbol + "([\\s\\w\\\\]|$)");
+        }
         if (line.regexCount(regex) > 1) {
             continue;
         }
-        let colonIndex = line.regexIndexOf(regex);
+        let colonIndex: number;
+        if (symbol == "direction") {
+            colonIndex = indexOfGroup(regex, line, 4);
+        }
+        else {
+            colonIndex = line.regexIndexOf(regex);
+        }
         if (colonIndex > 0) {
             maxSymbolIndex = Math.max(maxSymbolIndex, colonIndex);
             symbolIndices[i] = colonIndex;

tests/VHDLFormatter.test.ts

@@ -65,6 +65,36 @@ describe('VHDLFormatter', function () {
         let result = beautify(input, settings);
         expect(result).toBe(input);
     });
+
+    it('align in, out, inout, buffer', function () {
+        let settings = GetDefaultSettings();
+        settings.SignAlignSettings.isAll = true;
+        let input = "Incr, Load, Clock : IN     BIT;\r\nCarry             : OUT    BIT;\r\nData_Out          : BUFFER bit_vector(7 DOWNTO 0);\r\nData_In           : IN     bit_vector(7 DOWNTO 0)";
+        let result = beautify(input, settings);
+        expect(result).toBe(input);
+    });
+
+    it('align sign in PORT & GENERIC', function () {
+        let new_line_after_symbols: NewLineSettings = new NewLineSettings();
+        new_line_after_symbols.newLineAfter = ["then", ";"];
+        let settings = getDefaultBeautifierSettings(new_line_after_symbols);
+        settings.SignAlignSettings = new signAlignSettings(true, false, "global", ["PORT", "GENERIC"]);
+        let input = "entity p is\r\n  generic\r\n  (\r\n    -- INCLK\r\n    INCLK0_INPUT_FREQUENCY  : natural;\r\n\r\n    -- CLK1\r\n    CLK1_DIVIDE_BY          : natural := 1;\r\n    CLK1_MULTIPLY_BY        : unnatural:= 1;\r\n    CLK1_PHASE_SHIFT        : string := \"0\"\r\n  );\r\n	port\r\n	(\r\n		inclk0	: in bit  := '0';\r\n		c0		    : out bit;\r\n		c1		    : out bit \r\n	);\r\nEND pll;";
+        let expected = "ENTITY p IS\r\n    GENERIC (\r\n        -- INCLK\r\n        INCLK0_INPUT_FREQUENCY : NATURAL;\r\n\r\n        -- CLK1\r\n        CLK1_DIVIDE_BY         : NATURAL   := 1;\r\n        CLK1_MULTIPLY_BY       : unnatural := 1;\r\n        CLK1_PHASE_SHIFT       : STRING    := \"0\"\r\n    );\r\n    PORT (\r\n        inclk0 : IN  BIT := '0';\r\n        c0     : OUT BIT;\r\n        c1     : OUT BIT\r\n    );\r\nEND pll;";
+        let result = beautify(input, settings);
+        expect(result).toBe(expected);
+    });
+    
+    it('align signs in all places', function () {
+        let setting = getDefaultBeautifierSettings(new NewLineSettings());
+        setting.SignAlignSettings = new signAlignSettings(false, true, "", []);
+        setting.NewLineSettings.newLineAfter = ["then", ";", "generic", "port"];
+        setting.NewLineSettings.noNewLineAfter = [];
+        let input = "entity a is\r\n    port ( w  : in  bit;\r\n           w_s : out bit; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n    process ( w )\r\n    variable t : bit;\r\n    variable bcd     : bit;\r\nbegin\r\n    b(2 downto 0) := w(7 downto 5) ;\r\n    t         := w(4 downto 0) ;\r\n    w_s <= b(11 downto 8) ;\r\n    w <= b(3  downto 0) ;\r\nend process ;\r\nend b;";
+        let expected = "ENTITY a IS\r\n    PORT\r\n    (\r\n        w   : IN  BIT;\r\n        w_s : OUT BIT;\r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n        VARIABLE t   : BIT;\r\n        VARIABLE bcd : BIT;\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
+        let result = beautify(input, setting);
+        expect(result).toBe(expected);
+    });
 });
 
 function GetDefaultSettings(indentation: string = "    "): BeautifierSettings {

tests/VHDLFormatterUnitTests.ts

@@ -789,7 +789,6 @@ function IntegrationTest() {
 
     IntegrationTest5();
     IntegrationTest6();
-    IntegrationTest7();
 
     input = 'if a(3 downto 0) > "0100" then\r\na(3 downto 0) := a(3 downto 0) + "0011" ;\r\nend if ;';
     expected = 'IF a(3 DOWNTO 0) > "0100" THEN\r\n    a(3 DOWNTO 0) := a(3 DOWNTO 0) + "0011";\r\nEND IF;';
@@ -851,15 +850,6 @@ function IntegrationTest() {
     actual = beautify(input, newSettings);
     assertAndCountTest("Double BEGIN", expected, actual);
 
-    let newSettings2 = deepCopy(newSettings);
-    newSettings2.SignAlignSettings = new signAlignSettings(false, true, "", []);
-    newSettings2.NewLineSettings.newLineAfter = ["then", ";", "generic", "port"];
-    newSettings2.NewLineSettings.noNewLineAfter = [];
-    input = "entity a is\r\n    port ( w  : in  std_logic_vector (7 downto 0) ;\r\n           w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n    process ( w )\r\n    variable t : std_logic_vector (4 downto 0) ;\r\n    variable bcd     : std_logic_vector (11 downto 0) ;\r\nbegin\r\n    b(2 downto 0) := w(7 downto 5) ;\r\n    t         := w(4 downto 0) ;\r\n    w_s <= b(11 downto 8) ;\r\n    w <= b(3  downto 0) ;\r\nend process ;\r\nend b ;";
-    expected = "ENTITY a IS\r\n    PORT\r\n    (\r\n        w   : IN std_logic_vector (7 DOWNTO 0);\r\n        w_s : OUT std_logic_vector (3 DOWNTO 0);\r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n        VARIABLE t   : std_logic_vector (4 DOWNTO 0);\r\n        VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
-    actual = beautify(input, newSettings2);
-    assertAndCountTest("Align signs in all places", expected, actual);
-
     IntegrationTest23();
     IntegrationTest24();
     IntegrationTest25();
@@ -1472,17 +1462,6 @@ function IntegrationTest6() {
     assertAndCountTest("Sign align in PORT & new line after MAP", expected, actual);
 }
 
-function IntegrationTest7() {
-    let new_line_after_symbols: NewLineSettings = new NewLineSettings();
-    new_line_after_symbols.newLineAfter = ["then", ";"];
-    let settings = getDefaultBeautifierSettings(new_line_after_symbols);
-    settings.SignAlignSettings = new signAlignSettings(true, false, "global", ["PORT", "GENERIC"]);
-    let input = "entity p is\r\n  generic\r\n  (\r\n    -- INCLK\r\n    INCLK0_INPUT_FREQUENCY  : natural;\r\n\r\n    -- CLK1\r\n    CLK1_DIVIDE_BY          : natural := 1;\r\n    CLK1_MULTIPLY_BY        : unnatural:= 1;\r\n    CLK1_PHASE_SHIFT        : string := \"0\"\r\n  );\r\n	port\r\n	(\r\n		inclk0	: in std_logic  := '0';\r\n		c0		    : out std_logic ;\r\n		c1		    : out std_logic \r\n	);\r\nEND pll;";
-    let expected = "ENTITY p IS\r\n    GENERIC (\r\n        -- INCLK\r\n        INCLK0_INPUT_FREQUENCY : NATURAL;\r\n\r\n        -- CLK1\r\n        CLK1_DIVIDE_BY         : NATURAL   := 1;\r\n        CLK1_MULTIPLY_BY       : unnatural := 1;\r\n        CLK1_PHASE_SHIFT       : STRING    := \"0\"\r\n    );\r\n    PORT (\r\n        inclk0 : IN std_logic := '0';\r\n        c0     : OUT std_logic;\r\n        c1     : OUT std_logic\r\n    );\r\nEND pll;";
-    let actual = beautify(input, settings);
-    assertAndCountTest("Sign align in PORT & GENERIC", expected, actual);
-}
-
 function IntegrationTest2() {
     let new_line_after_symbols: NewLineSettings = new NewLineSettings();
     new_line_after_symbols.newLineAfter = ["then", ";"];