letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
letactual=beautify(input,settings);
letactual=beautify(input,settings);
@ -911,173 +911,124 @@ function IntegrationTest() {
letinput="PACKAGE p IS\r\n TYPE int_array IS ARRAY (INTEGER RANGE <>) OF INTEGER;\r\n TYPE ten_ints IS ARRAY (1 TO 10) OF INTEGER;\r\n TYPE chars IS (A, B, C);\r\n TYPE char_counts IS ARRAY (chars) OF INTEGER;\r\n TYPE two_d IS ARRAY (1 TO 3, 4 TO 6) OF INTEGER;\r\n TYPE ab_chars IS ARRAY (chars RANGE A TO B) OF INTEGER;\r\nEND PACKAGE;";
letinput="PACKAGE p IS\r\n TYPE int_array IS ARRAY (INTEGER RANGE <>) OF INTEGER;\r\n TYPE ten_ints IS ARRAY (1 TO 10) OF INTEGER;\r\n TYPE chars IS (A, B, C);\r\n TYPE char_counts IS ARRAY (chars) OF INTEGER;\r\n TYPE two_d IS ARRAY (1 TO 3, 4 TO 6) OF INTEGER;\r\n TYPE ab_chars IS ARRAY (chars RANGE A TO B) OF INTEGER;\r\nEND PACKAGE;";
letinput="ARCHITECTURE a OF e IS\r\n ATTRIBUTE foo : INTEGER;\r\n ATTRIBUTE foo OF x : SIGNAL IS 5;\r\n ATTRIBUTE foo OF x : COMPONENT IS 5;\r\n ATTRIBUTE foo OF x : LABEL IS 6;\r\n ATTRIBUTE foo OF x : TYPE IS 4;\r\nBEGIN\r\n ASSERT x'foo(5);\r\nEND ARCHITECTURE;";
letinput="ARCHITECTURE a OF e IS\r\n ATTRIBUTE foo : INTEGER;\r\n ATTRIBUTE foo OF x : SIGNAL IS 5;\r\n ATTRIBUTE foo OF x : COMPONENT IS 5;\r\n ATTRIBUTE foo OF x : LABEL IS 6;\r\n ATTRIBUTE foo OF x : TYPE IS 4;\r\nBEGIN\r\n ASSERT x'foo(5);\r\nEND ARCHITECTURE;";
letinput='PACKAGE bitstring IS\r\n CONSTANT x : t := X"1234";\r\n CONSTANT y : t := O"1234";\r\n CONSTANT z : t := X"ab";\r\n CONSTANT b : t := B"101";\r\n CONSTANT c : t := x"f";\r\n CONSTANT d : t := X"a_b";\r\nEND PACKAGE;\r\nPACKAGE bitstring_error IS\r\n CONSTANT e1 : t := O"9"; -- Error\r\nEND PACKAGE;';
letinput='PACKAGE bitstring IS\r\n CONSTANT x : t := X"1234";\r\n CONSTANT y : t := O"1234";\r\n CONSTANT z : t := X"ab";\r\n CONSTANT b : t := B"101";\r\n CONSTANT c : t := x"f";\r\n CONSTANT d : t := X"a_b";\r\nEND PACKAGE;\r\nPACKAGE bitstring_error IS\r\n CONSTANT e1 : t := O"9"; -- Error\r\nEND PACKAGE;';
letinput='ARCHITECTURE a OF e IS\r\nBEGIN\r\n b : BLOCK IS\r\n BEGIN\r\n END BLOCK;\r\n c : BLOCK IS\r\n SIGNAL x : INTEGER;\r\n SIGNAL y : real;\r\n BEGIN\r\n x <= y;\r\n END BLOCK;\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF e IS\r\nBEGIN\r\n b : BLOCK IS\r\n BEGIN\r\n END BLOCK;\r\n c : BLOCK IS\r\n SIGNAL x : INTEGER;\r\n SIGNAL y : real;\r\n BEGIN\r\n x <= y;\r\n END BLOCK;\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE foo OF bar IS\r\n SIGNAL \\foo bar\\ : INTEGER;\r\n SIGNAL \\a\\\\b\\ : INTEGER;\r\n SIGNAL \\Thing!!! \\ : INTEGER;\r\n SIGNAL \\name\\ : INTEGER;\r\n SIGNAL name : INTEGER;\r\nBEGIN\r\n \\foo.bar.baz\\ <= \\hello\\;\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE foo OF bar IS\r\n SIGNAL \\foo bar\\ : INTEGER;\r\n SIGNAL \\a\\\\b\\ : INTEGER;\r\n SIGNAL \\Thing!!! \\ : INTEGER;\r\n SIGNAL \\name\\ : INTEGER;\r\n SIGNAL name : INTEGER;\r\nBEGIN\r\n \\foo.bar.baz\\ <= \\hello\\;\r\nEND ARCHITECTURE;';
letinput='PACKAGE func IS\r\n FUNCTION add(x, y : INTEGER; y : IN INTEGER) RETURN INTEGER;\r\n IMPURE FUNCTION naughty RETURN INTEGER;\r\n FUNCTION "+"(x, y : INTEGER) RETURN INTEGER;\r\nEND PACKAGE;';
letinput='PACKAGE func IS\r\n FUNCTION add(x, y : INTEGER; y : IN INTEGER) RETURN INTEGER;\r\n IMPURE FUNCTION naughty RETURN INTEGER;\r\n FUNCTION "+"(x, y : INTEGER) RETURN INTEGER;\r\nEND PACKAGE;';
letinput='ARCHITECTURE a OF g IS\r\nBEGIN\r\n\r\n g1 : IF foo GENERATE\r\n SIGNAL x : INTEGER;\r\n BEGIN\r\n x <= 5;\r\n END GENERATE;\r\n\r\n g2 : IF bar GENERATE\r\n g2a : IF x < 5 GENERATE\r\n g <= 7;\r\n END GENERATE;\r\n END GENERATE;\r\n\r\n g3 : FOR i IN 1 TO 40 GENERATE\r\n SIGNAL x : INTEGER;\r\n BEGIN\r\n f <= h;\r\n END GENERATE;\r\n\r\n g4 : FOR i IN x\'RANGE GENERATE\r\n END GENERATE;\r\n\r\n g5 : FOR i IN x\'RANGE GENERATE\r\n BEGIN\r\n END GENERATE;\r\n\r\n g6 : FOR i IN 1 TO 3 GENERATE\r\n COMPONENT sub_ent IS\r\n PORT (val : OUT NATURAL);\r\n END COMPONENT sub_ent; -- OK\r\n BEGIN\r\n END GENERATE;\r\n\r\n g7 : IF true GENERATE\r\n PROCEDURE doit IS -- OK\r\n BEGIN\r\n write(OUTPUT, "OK." & LF);\r\n END PROCEDURE doit;\r\n BEGIN\r\n END GENERATE g7;\r\n\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF g IS\r\nBEGIN\r\n\r\n g1 : IF foo GENERATE\r\n SIGNAL x : INTEGER;\r\n BEGIN\r\n x <= 5;\r\n END GENERATE;\r\n\r\n g2 : IF bar GENERATE\r\n g2a : IF x < 5 GENERATE\r\n g <= 7;\r\n END GENERATE;\r\n END GENERATE;\r\n\r\n g3 : FOR i IN 1 TO 40 GENERATE\r\n SIGNAL x : INTEGER;\r\n BEGIN\r\n f <= h;\r\n END GENERATE;\r\n\r\n g4 : FOR i IN x\'RANGE GENERATE\r\n END GENERATE;\r\n\r\n g5 : FOR i IN x\'RANGE GENERATE\r\n BEGIN\r\n END GENERATE;\r\n\r\n g6 : FOR i IN 1 TO 3 GENERATE\r\n COMPONENT sub_ent IS\r\n PORT (val : OUT NATURAL);\r\n END COMPONENT sub_ent; -- OK\r\n BEGIN\r\n END GENERATE;\r\n\r\n g7 : IF true GENERATE\r\n PROCEDURE doit IS -- OK\r\n BEGIN\r\n write(OUTPUT, "OK." & LF);\r\n END PROCEDURE doit;\r\n BEGIN\r\n END GENERATE g7;\r\n\r\nEND ARCHITECTURE;';
letinput='ENTITY ent IS\r\nEND ENTITY;\r\n\r\nARCHITECTURE a OF ent IS\r\nBEGIN\r\n main : PROCESS\r\n BEGIN\r\n REPORT """""";\r\n WAIT;\r\n END PROCESS;\r\nEND ARCHITECTURE;';
letinput='ENTITY ent IS\r\nEND ENTITY;\r\n\r\nARCHITECTURE a OF ent IS\r\nBEGIN\r\n main : PROCESS\r\n BEGIN\r\n REPORT """""";\r\n WAIT;\r\n END PROCESS;\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\nBEGIN\r\n\r\n -- Wait statements\r\n PROCESS IS\r\n BEGIN\r\n WAIT FOR 1 ns;\r\n block_forever : WAIT;\r\n WAIT ON x;\r\n WAIT ON x, y, z(1 DOWNTO 0);\r\n WAIT ON w(1) FOR 2 ns;\r\n WAIT UNTIL x = 3;\r\n WAIT UNTIL y = x FOR 5 ns;\r\n WAIT ON x UNTIL x = 2 FOR 1 ns;\r\n END PROCESS;\r\n\r\n -- Blocking assignment\r\n PROCESS IS\r\n VARIABLE a : INTEGER;\r\n BEGIN\r\n a := 2;\r\n a := a + (a * 3);\r\n END PROCESS;\r\n\r\n -- Assert and report\r\n PROCESS IS\r\n BEGIN\r\n ASSERT true;\r\n ASSERT false SEVERITY note;\r\n ASSERT 1 > 2 REPORT "oh no" SEVERITY failure;\r\n REPORT "hello";\r\n REPORT "boo" SEVERITY error;\r\n END PROCESS;\r\n\r\n -- Function calls\r\n PROCESS IS\r\n BEGIN\r\n x := foo(1, 2, 3);\r\n a := "ABS"(b);\r\n END PROCESS;\r\n\r\n -- If\r\n PROCESS IS\r\n BEGIN\r\n IF true THEN\r\n x := 1;\r\n END IF;\r\n test : IF true THEN\r\n x := y;\r\n END IF test;\r\n IF x > 2 THEN\r\n x := 5;\r\n ELSE\r\n y := 2;\r\n END IF;\r\n IF x > 3 THEN\r\n NULL;\r\n ELSIF x > 5 THEN\r\n NULL;\r\n ELSIF true THEN\r\n NULL;\r\n ELSE\r\n x := 2;\r\n END IF;\r\n END PROCESS;\r\n\r\n -- Null\r\n PROCESS IS\r\n BEGIN\r\n NULL;\r\n END PROCESS;\r\n\r\n -- Return\r\n PROCESS IS\r\n BEGIN\r\n RETURN 4 * 4;\r\n END PROCESS;\r\n\r\n -- While\r\n PROCESS IS\r\n BEGIN\r\n WHILE n > 0 LOOP\r\n n := n - 1;\r\n END LOOP;\r\n LOOP\r\n NULL;\r\n END LOOP;\r\n END PROCESS;\r\n\r\n -- Delayed assignment\r\n PROCESS IS\r\n BEGIN\r\n x <= 4 AFTER 5 ns;\r\n x <= 5 AFTER 1 ns, 7 AFTER 8 ns;\r\n x <= 5, 7 AFTER 8 ns;\r\n x <= INERTIAL 5;\r\n x <= TRANSPORT 4 AFTER 2 ns;\r\n x <= REJECT 4 ns INERTIAL 6 AFTER 10 ns;\r\n END PROCESS;\r\n\r\n -- For\r\n PROCESS IS\r\n BEGIN\r\n FOR i IN 0 TO 10 LOOP\r\n NULL;\r\n END LOOP;\r\n FOR i IN foo\'RANGE LOOP\r\n NULL;\r\n END LOOP;\r\n END PROCESS;\r\n\r\n -- Exit\r\n PROCESS IS\r\n BEGIN\r\n EXIT;\r\n EXIT WHEN x = 1;\r\n END PROCESS;\r\n\r\n -- Procedure call\r\n PROCESS IS\r\n BEGIN\r\n foo(x, y, 1);\r\n bar;\r\n foo(a => 1, b => 2, 3);\r\n END PROCESS;\r\n\r\n -- Case\r\n PROCESS IS\r\n BEGIN\r\n CASE x IS\r\n WHEN 1 =>\r\n NULL;\r\n WHEN 2 =>\r\n NULL;\r\n WHEN 3 | 4 =>\r\n NULL;\r\n WHEN OTHERS =>\r\n NULL;\r\n END CASE;\r\n END PROCESS;\r\n\r\n -- Next\r\n PROCESS IS\r\n BEGIN\r\n NEXT;\r\n NEXT WHEN foo = 5;\r\n END PROCESS;\r\n\r\n -- Signal assignment to aggregate\r\n PROCESS IS\r\n BEGIN\r\n (x, y, z) <= foo;\r\n END PROCESS;\r\n\r\n -- Case statement range bug\r\n PROCESS IS\r\n BEGIN\r\n CASE f IS\r\n WHEN 1 =>\r\n FOR i IN x\'RANGE LOOP\r\n END LOOP;\r\n END CASE;\r\n END PROCESS;\r\n\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\nBEGIN\r\n\r\n -- Wait statements\r\n PROCESS IS\r\n BEGIN\r\n WAIT FOR 1 ns;\r\n block_forever : WAIT;\r\n WAIT ON x;\r\n WAIT ON x, y, z(1 DOWNTO 0);\r\n WAIT ON w(1) FOR 2 ns;\r\n WAIT UNTIL x = 3;\r\n WAIT UNTIL y = x FOR 5 ns;\r\n WAIT ON x UNTIL x = 2 FOR 1 ns;\r\n END PROCESS;\r\n\r\n -- Blocking assignment\r\n PROCESS IS\r\n VARIABLE a : INTEGER;\r\n BEGIN\r\n a := 2;\r\n a := a + (a * 3);\r\n END PROCESS;\r\n\r\n -- Assert and report\r\n PROCESS IS\r\n BEGIN\r\n ASSERT true;\r\n ASSERT false SEVERITY note;\r\n ASSERT 1 > 2 REPORT "oh no" SEVERITY failure;\r\n REPORT "hello";\r\n REPORT "boo" SEVERITY error;\r\n END PROCESS;\r\n\r\n -- Function calls\r\n PROCESS IS\r\n BEGIN\r\n x := foo(1, 2, 3);\r\n a := "ABS"(b);\r\n END PROCESS;\r\n\r\n -- If\r\n PROCESS IS\r\n BEGIN\r\n IF true THEN\r\n x := 1;\r\n END IF;\r\n test : IF true THEN\r\n x := y;\r\n END IF test;\r\n IF x > 2 THEN\r\n x := 5;\r\n ELSE\r\n y := 2;\r\n END IF;\r\n IF x > 3 THEN\r\n NULL;\r\n ELSIF x > 5 THEN\r\n NULL;\r\n ELSIF true THEN\r\n NULL;\r\n ELSE\r\n x := 2;\r\n END IF;\r\n END PROCESS;\r\n\r\n -- Null\r\n PROCESS IS\r\n BEGIN\r\n NULL;\r\n END PROCESS;\r\n\r\n -- Return\r\n PROCESS IS\r\n BEGIN\r\n RETURN 4 * 4;\r\n END PROCESS;\r\n\r\n -- While\r\n PROCESS IS\r\n BEGIN\r\n WHILE n > 0 LOOP\r\n n := n - 1;\r\n END LOOP;\r\n LOOP\r\n NULL;\r\n END LOOP;\r\n END PROCESS;\r\n\r\n -- Delayed assignment\r\n PROCESS IS\r\n BEGIN\r\n x <= 4 AFTER 5 ns;\r\n x <= 5 AFTER 1 ns, 7 AFTER 8 ns;\r\n x <= 5, 7 AFTER 8 ns;\r\n x <= INERTIAL 5;\r\n x <= TRANSPORT 4 AFTER 2 ns;\r\n x <= REJECT 4 ns INERTIAL 6 AFTER 10 ns;\r\n END PROCESS;\r\n\r\n -- For\r\n PROCESS IS\r\n BEGIN\r\n FOR i IN 0 TO 10 LOOP\r\n NULL;\r\n END LOOP;\r\n FOR i IN foo\'RANGE LOOP\r\n NULL;\r\n END LOOP;\r\n END PROCESS;\r\n\r\n -- Exit\r\n PROCESS IS\r\n BEGIN\r\n EXIT;\r\n EXIT WHEN x = 1;\r\n END PROCESS;\r\n\r\n -- Procedure call\r\n PROCESS IS\r\n BEGIN\r\n foo(x, y, 1);\r\n bar;\r\n foo(a => 1, b => 2, 3);\r\n END PROCESS;\r\n\r\n -- Case\r\n PROCESS IS\r\n BEGIN\r\n CASE x IS\r\n WHEN 1 =>\r\n NULL;\r\n WHEN 2 =>\r\n NULL;\r\n WHEN 3 | 4 =>\r\n NULL;\r\n WHEN OTHERS =>\r\n NULL;\r\n END CASE;\r\n END PROCESS;\r\n\r\n -- Next\r\n PROCESS IS\r\n BEGIN\r\n NEXT;\r\n NEXT WHEN foo = 5;\r\n END PROCESS;\r\n\r\n -- Signal assignment to aggregate\r\n PROCESS IS\r\n BEGIN\r\n (x, y, z) <= foo;\r\n END PROCESS;\r\n\r\n -- Case statement range bug\r\n PROCESS IS\r\n BEGIN\r\n CASE f IS\r\n WHEN 1 =>\r\n FOR i IN x\'RANGE LOOP\r\n END LOOP;\r\n END CASE;\r\n END PROCESS;\r\n\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\n FOR x : y USE ENTITY work.foo;\r\n FOR x1, x2 : y USE ENTITY work.foo;\r\n FOR x : y USE ENTITY work.foo(bar);\r\n FOR x : y USE ENTITY work.foo(bar)\r\n GENERIC MAP(a => 1)\r\n PORT MAP(b => g);\r\n FOR ALL : y USE CONFIGURATION yah;\r\n FOR OTHERS : y USE OPEN;\r\nBEGIN\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\n FOR x : y USE ENTITY work.foo;\r\n FOR x1, x2 : y USE ENTITY work.foo;\r\n FOR x : y USE ENTITY work.foo(bar);\r\n FOR x : y USE ENTITY work.foo(bar)\r\n GENERIC MAP(a => 1)\r\n PORT MAP(b => g);\r\n FOR ALL : y USE CONFIGURATION yah;\r\n FOR OTHERS : y USE OPEN;\r\nBEGIN\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\n TYPE my_int IS RANGE 0 TO 100;\r\n SIGNAL x : my_int := 2;\r\n\r\n TYPE resistance IS RANGE 0 TO 10000000\r\n UNITS\r\n ohm;\r\n kohm = 1000 ohm;\r\n Mohm = 1000 kohm;\r\n END UNITS;\r\n SIGNAL r : resistance := 100 ohm;\r\n\r\n SUBTYPE big_r IS resistance RANGE 1000 TO 2000;\r\n\r\n SUBTYPE my_small_int IS my_int RANGE 0 TO 5;\r\n\r\n SUBTYPE foo IS my_int RANGE 2 TO my_int\'high;\r\n\r\n SUBTYPE rint IS resolved my_int;\r\n\r\n TYPE p IS ACCESS my_int;\r\n\r\n TYPE f IS FILE OF my_int;\r\n\r\n FILE f1 : f OPEN READ_MODE IS "foo";\r\n\r\n FILE f2 : f IS "bar";\r\n\r\n FILE f3 : f;\r\n\r\n TYPE r1 IS RECORD\r\n a : INTEGER;\r\n b : INTEGER;\r\n c : foo(1 TO 5);\r\n END RECORD;\r\n\r\n FILE f4 : f IS OUT "bar"; -- VHDL-87 compat\r\n\r\n FILE f5 : f IS IN "bar"; -- VHDL-87 compat\r\n\r\n TYPE r2 IS RECORD\r\n x : INTEGER;\r\n END RECORD r2;\r\n\r\nBEGIN\r\n\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE a OF b IS\r\n TYPE my_int IS RANGE 0 TO 100;\r\n SIGNAL x : my_int := 2;\r\n\r\n TYPE resistance IS RANGE 0 TO 10000000\r\n UNITS\r\n ohm;\r\n kohm = 1000 ohm;\r\n Mohm = 1000 kohm;\r\n END UNITS;\r\n SIGNAL r : resistance := 100 ohm;\r\n\r\n SUBTYPE big_r IS resistance RANGE 1000 TO 2000;\r\n\r\n SUBTYPE my_small_int IS my_int RANGE 0 TO 5;\r\n\r\n SUBTYPE foo IS my_int RANGE 2 TO my_int\'high;\r\n\r\n SUBTYPE rint IS resolved my_int;\r\n\r\n TYPE p IS ACCESS my_int;\r\n\r\n TYPE f IS FILE OF my_int;\r\n\r\n FILE f1 : f OPEN READ_MODE IS "foo";\r\n\r\n FILE f2 : f IS "bar";\r\n\r\n FILE f3 : f;\r\n\r\n TYPE r1 IS RECORD\r\n a : INTEGER;\r\n b : INTEGER;\r\n c : foo(1 TO 5);\r\n END RECORD;\r\n\r\n FILE f4 : f IS OUT "bar"; -- VHDL-87 compat\r\n\r\n FILE f5 : f IS IN "bar"; -- VHDL-87 compat\r\n\r\n TYPE r2 IS RECORD\r\n x : INTEGER;\r\n END RECORD r2;\r\n\r\nBEGIN\r\n\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE test3 OF test IS\r\n COMPONENT comp IS PORT (a : BOOLEAN);\r\n END COMPONENT;\r\n SIGNAL s_ok : BOOLEAN;\r\nBEGIN\r\n comp PORT MAP(a => s_ok); -- unlabeled component instantiation\r\nEND ARCHITECTURE;';
letinput='ARCHITECTURE test3 OF test IS\r\n COMPONENT comp IS PORT (a : BOOLEAN);\r\n END COMPONENT;\r\n SIGNAL s_ok : BOOLEAN;\r\nBEGIN\r\n comp PORT MAP(a => s_ok); -- unlabeled component instantiation\r\nEND ARCHITECTURE;';
letinput='ENTITY bar IS\r\nEND ENTITY bar;\r\nENTITY \\foo\\ IS\r\n PORT (test : IN BIT);\r\nEND ENTITY \\foo\\;\r\nARCHITECTURE structural OF \\foo\\ IS\r\nBEGIN -- architecture structural\r\nEND ARCHITECTURE structural;\r\nARCHITECTURE structural OF bar IS\r\n SIGNAL test : BIT;\r\nBEGIN -- architecture structural\r\n foo_1 : ENTITY work.\\foo\\\r\n PORT MAP(test => test);\r\nEND ARCHITECTURE structural;';
letinput='ENTITY bar IS\r\nEND ENTITY bar;\r\nENTITY \\foo\\ IS\r\n PORT (test : IN BIT);\r\nEND ENTITY \\foo\\;\r\nARCHITECTURE structural OF \\foo\\ IS\r\nBEGIN -- architecture structural\r\nEND ARCHITECTURE structural;\r\nARCHITECTURE structural OF bar IS\r\n SIGNAL test : BIT;\r\nBEGIN -- architecture structural\r\n foo_1 : ENTITY work.\\foo\\\r\n PORT MAP(test => test);\r\nEND ARCHITECTURE structural;';
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";