support PORT sign align

VHDLFormatter.html

@@ -188,7 +188,7 @@
         <input type="checkbox" id="check_alias">Check ALIAS (every long name is replaced with ALIAS)</label>
     <br>
     <label>
-        <input type="checkbox" id="sign_align">Align signs in PORT()</label>
+        <input type="checkbox" id="sign_align">Align signs in PORT() GENERIC()</label>
     <br>
     <label>
         <input type="checkbox" id="sign_align_all">Align signs in all places</label>
@@ -309,7 +309,9 @@
 
             var newLineSettingsDict = {};
             newLineSettingsDict["generic"] = new_line_after_generic;
+            newLineSettingsDict["generic map"] = new_line_after_generic;
             newLineSettingsDict["port"] = new_line_after_port;
+            newLineSettingsDict["port map"] = new_line_after_port;
             newLineSettingsDict[";"] = new_line_after_semicolon;
             newLineSettingsDict["then"] = new_line_after_then;
             newLineSettingsDict["else"] = new_line_after_else;

VHDLFormatter.js

@@ -50,6 +50,9 @@ function fetchHeader(url, wch) {
         return "";
     }
 }
+String.prototype.count = function (text) {
+    return this.split(text).length - 1;
+};
 String.prototype.regexStartsWith = function (pattern) {
     var searchResult = this.search(pattern);
     return searchResult == 0;
@@ -238,7 +241,7 @@ class BeautifierSettings {
         this.RemoveComments = removeComments;
         this.RemoveAsserts = removeReport;
         this.CheckAlias = checkAlias;
-        this.SignAlign = signAlign;
+        this.SignAlignRegional = signAlign;
         this.SignAlignAll = signAlignAll;
         this.KeywordCase = keywordCase;
         this.Indentation = indentation;
@@ -272,6 +275,13 @@ function beautify(input, settings) {
     input = arr.join("\r\n");
     input = input.replace(/(PORT|PROCESS|GENERIC)[\s]*\(/g, '$1 (');
     input = SetNewLinesAfterSymbols(input, settings.NewLineSettings);
+    arr = input.split("\r\n");
+    let quotes = EscapeQuotes(arr);
+    if (settings.RemoveAsserts) {
+        RemoveAsserts(arr); //RemoveAsserts must be after EscapeQuotes
+    }
+    ApplyNoNewLineAfter(arr, settings.NewLineSettings.noNewLineAfter);
+    input = arr.join("\r\n");
     //input = beautify2(input, settings);
     //new
     input = input.replace(/([a-zA-Z0-9\); ])\);(@@comments[0-9]+)?@@end/g, '$1\r\n);$2@@end');
@@ -283,8 +293,9 @@ function beautify(input, settings) {
     input = input.replace(/([\(\)])[ ]?(THEN)/gi, '$1 $2');
     input = input.replace(/(^|[\(\)])[ ]?(AND|OR|XOR|XNOR)[ ]*([\(])/g, '$1 $2 $3');
     input = input.replace(/ ([\-\*\/=+<>])[ ]*([\-\*\/=+<>]) /g, " $1$2 ");
-    input = input.replace(/\r\n[ \t]+--\r\n/g, "\r\n");
+    //input = input.replace(/\r\n[ \t]+--\r\n/g, "\r\n");
     input = input.replace(/[ ]+/g, ' ');
+    input = input.replace(/[ \t]+\r\n/g, "\r\n");
     input = input.replace(/\r\n\r\n\r\n/g, '\r\n');
     input = input.replace(/[\r\n\s]+$/g, '');
     input = input.replace(/[ \t]+\)/g, ')');
@@ -293,6 +304,9 @@ function beautify(input, settings) {
     beautify3(arr, result, settings, 0, 0);
     arr = FormattedLineToString(result, settings.Indentation);
     input = arr.join("\r\n");
+    for (var k = 0; k < quotes.length; k++) {
+        input = input.replace(ILQuotesPrefix + k, quotes[k]);
+    }
     for (var k = 0; k < commentsIndex; k++) {
         input = input.replace(ILCommentPrefix + k, comments[k]);
     }
@@ -315,7 +329,12 @@ function FormattedLineToString(arr, indentation) {
     }
     arr.forEach(i => {
         if (i instanceof FormattedLine) {
-            result.push((Array(i.Indent + 1).join(indentation)) + i.Line);
+            if (i.Line.length > 0) {
+                result.push((Array(i.Indent + 1).join(indentation)) + i.Line);
+            }
+            else {
+                result.push("");
+            }
         }
         else {
             result = result.concat(FormattedLineToString(i, indentation));
@@ -324,8 +343,113 @@ function FormattedLineToString(arr, indentation) {
     return result;
 }
 exports.FormattedLineToString = FormattedLineToString;
-function beautifyCaseBlock(inputs, result, settings, startIndex, indent, isFirstKeyWord) {
-    if (!inputs[startIndex].regexStartsWith(/(CASE)([\s]|$)/)) {
+function GetCloseparentheseEndIndex(inputs, startIndex) {
+    let openParentheseCount = 0;
+    let closeParentheseCount = 0;
+    for (let i = startIndex; i < inputs.length; i++) {
+        let input = inputs[i];
+        openParentheseCount += input.count("(");
+        closeParentheseCount += input.count(")");
+        if (openParentheseCount > 0
+            && openParentheseCount <= closeParentheseCount) {
+            return i;
+        }
+    }
+    return startIndex;
+}
+function beautifyPortGenericBlock(inputs, result, settings, startIndex, indent, mode) {
+    let firstLine = inputs[startIndex];
+    let regex = new RegExp("[\\w\\s:]*(" + mode + ")([\\s]|$)");
+    if (!firstLine.regexStartsWith(regex)) {
+        return startIndex;
+    }
+    let firstLineHasParenthese = firstLine.indexOf("(") >= 0;
+    let hasParenthese = firstLineHasParenthese;
+    let blockBodyStartIndex = startIndex;
+    let secondLineHasParenthese = inputs[startIndex + 1].startsWith("(");
+    if (secondLineHasParenthese) {
+        hasParenthese = true;
+        blockBodyStartIndex++;
+    }
+    let endIndex = hasParenthese ? GetCloseparentheseEndIndex(inputs, startIndex) : startIndex;
+    if (endIndex != startIndex && firstLineHasParenthese) {
+        inputs[startIndex] = inputs[startIndex].replace(/(PORT|GENERIC|PROCEDURE)([\w ]+)\(([\w\(\) ]+)/, '$1$2(\r\n$3');
+        let newInputs = inputs[startIndex].split("\r\n");
+        if (newInputs.length == 2) {
+            inputs[startIndex] = newInputs[0];
+            inputs.splice(startIndex + 1, 0, newInputs[1]);
+            endIndex++;
+        }
+    }
+    else if (endIndex != startIndex && secondLineHasParenthese) {
+        inputs[startIndex + 1] = inputs[startIndex + 1].replace(/\(([\w\(\) ]+)/, '(\r\n$1');
+        let newInputs = inputs[startIndex + 1].split("\r\n");
+        if (newInputs.length == 2) {
+            inputs[startIndex + 1] = newInputs[0];
+            inputs.splice(startIndex + 2, 0, newInputs[1]);
+            endIndex++;
+        }
+    }
+    if (firstLineHasParenthese && inputs[startIndex].indexOf("MAP") > 0) {
+        inputs[startIndex] = inputs[startIndex].replace(/([^\w])(MAP)\s+\(/g, '$1$2(');
+    }
+    result.push(new FormattedLine(inputs[startIndex], indent));
+    if (secondLineHasParenthese) {
+        result.push(new FormattedLine(inputs[startIndex + 1], indent));
+    }
+    let blockBodyEndIndex = endIndex;
+    let i = beautify3(inputs, result, settings, blockBodyStartIndex + 1, indent + 1, endIndex);
+    if (inputs[i].startsWith(")")) {
+        result[i].Indent--;
+        blockBodyEndIndex--;
+    }
+    if (settings.SignAlignRegional) {
+        blockBodyStartIndex++;
+        SignAlignRegional(result, blockBodyStartIndex, blockBodyEndIndex);
+    }
+    return i;
+}
+exports.beautifyPortGenericBlock = beautifyPortGenericBlock;
+function SignAlignRegional(result, startIndex, endIndex) {
+    let maxSymbolIndex = {};
+    let allSymbolIndex = {};
+    for (let i = startIndex; i <= endIndex; i++) {
+        let line = result[i].Line;
+        SetSymbolIndices(line, ":", maxSymbolIndex, allSymbolIndex, i);
+        SetSymbolIndices(line, ":=", maxSymbolIndex, allSymbolIndex, i);
+        SetSymbolIndices(line, "=>", maxSymbolIndex, allSymbolIndex, i);
+    }
+    for (let key in maxSymbolIndex) {
+        let maxIndex = maxSymbolIndex[key];
+        for (let lineIndex in allSymbolIndex[key]) {
+            let symbolIndex = allSymbolIndex[key][lineIndex];
+            if (symbolIndex == maxIndex) {
+                continue;
+            }
+            let line = result[lineIndex].Line;
+            result[lineIndex].Line = line.substring(0, symbolIndex)
+                + (Array(maxIndex - symbolIndex + 1).join(" "))
+                + line.substring(symbolIndex);
+        }
+    }
+}
+exports.SignAlignRegional = SignAlignRegional;
+function SetSymbolIndices(line, symbol, maxSymbolIndex, allSymbolIndex, index) {
+    let regex = new RegExp("([\\s\\w]|^)" + symbol + "([\\s\\w]|$)");
+    let colonIndex = line.regexIndexOf(regex);
+    if (colonIndex > 0) {
+        if (maxSymbolIndex.hasOwnProperty(symbol)) {
+            maxSymbolIndex[symbol] = Math.max(maxSymbolIndex[symbol], colonIndex);
+        }
+        else {
+            maxSymbolIndex[symbol] = colonIndex;
+            allSymbolIndex[symbol] = {};
+        }
+        allSymbolIndex[symbol][index] = colonIndex;
+    }
+}
+function beautifyCaseBlock(inputs, result, settings, startIndex, indent) {
+    if (!inputs[startIndex].regexStartsWith(/(.+:\s*)?(CASE)([\s]|$)/)) {
         return startIndex;
     }
     result.push(new FormattedLine(inputs[startIndex], indent));
@@ -334,9 +458,9 @@ function beautifyCaseBlock(inputs, result, settings, startIndex, indent, isFirst
     return i;
 }
 exports.beautifyCaseBlock = beautifyCaseBlock;
-function beautify3(inputs, result, settings, startIndex, indent, isFirstKeyWord) {
+function beautify3(inputs, result, settings, startIndex, indent, endIndex) {
     let i;
-    let regexOneLineBlockKeyWords = new RegExp(/(PROCEDURE|FUNCTION|IMPURE FUNCTION)[^\w_](?!.+[^\w_]IS([^\w_]|$))/); //match PROCEDURE..; but not PROCEDURE .. IS;
+    let regexOneLineBlockKeyWords = new RegExp(/(PROCEDURE|FUNCTION|IMPURE FUNCTION)[^\w](?!.+[^\w]IS([^\w]|$))/); //match PROCEDURE..; but not PROCEDURE .. IS;
     let blockMidKeyWords = ["ELSE", "ELSIF", "WHEN", "BEGIN"];
     let blockStartsKeyWords = [
         "IF",
@@ -346,25 +470,37 @@ function beautify3(inputs, result, settings, startIndex, indent, isFirstKeyWord)
         "PACKAGE",
         "PROCESS",
         "POSTPONED PROCESS",
-        "(\\w+:\\s+PROCESS)",
+        "([\\w\\s]+:\\s*PROCESS)",
         "FUNCTION",
         "IMPURE FUNCTION",
         "(.+\\sPROTECTED)",
-        "COMPONENT"
+        "COMPONENT",
+        "ENTITY"
     ];
     let blockEndsKeyWords = ["END"];
     let newLineAfterKeyWordsStr = blockStartsKeyWords.join("|");
     let blockEndKeyWordsStr = blockEndsKeyWords.join("|");
     let blockMidKeyWordsStr = blockMidKeyWords.join("|");
-    let regexBlockMidKeyWords = new RegExp("(" + blockMidKeyWordsStr + ")([^\\w_]|$)");
-    let regexBlockStartsKeywords = new RegExp("(" + newLineAfterKeyWordsStr + ")([^\\w_]|$)");
-    let regexBlockEndsKeyWords = new RegExp("(" + blockEndKeyWordsStr + ")([^\\w_]|$)");
-    for (i = startIndex; i < inputs.length; i++) {
+    let regexBlockMidKeyWords = new RegExp("(" + blockMidKeyWordsStr + ")([^\\w]|$)");
+    let regexBlockStartsKeywords = new RegExp("(" + newLineAfterKeyWordsStr + ")([^\\w]|$)");
+    let regexBlockEndsKeyWords = new RegExp("(" + blockEndKeyWordsStr + ")([^\\w]|$)");
+    if (endIndex == null) {
+        endIndex = inputs.length - 1;
+    }
+    for (i = startIndex; i <= endIndex; i++) {
         let input = inputs[i].trim();
-        if (input.regexStartsWith(/(CASE)([\s]|$)/)) {
+        if (input.regexStartsWith(/(.+:\s*)?(CASE)([\s]|$)/)) {
             i = beautifyCaseBlock(inputs, result, settings, i, indent);
             continue;
         }
+        if (input.regexStartsWith(/[\w\s:]*PORT([\s]|$)/)) {
+            i = beautifyPortGenericBlock(inputs, result, settings, i, indent, "PORT");
+            continue;
+        }
+        if (input.regexStartsWith(/[\w\s:]*GENERIC([\s]|$)/)) {
+            i = beautifyPortGenericBlock(inputs, result, settings, i, indent, "GENERIC");
+            continue;
+        }
         result.push(new FormattedLine(input, indent));
         if (startIndex != 0
             && (input.regexStartsWith(regexBlockMidKeyWords))) {
@@ -712,7 +848,7 @@ function beautify2(input, settings) {
                     lastAlignedSign = "";
                 }
             }
-            else if (settings.SignAlign) {
+            else if (settings.SignAlignRegional) {
                 if (port_b && signAlignPos != "") {
                     if (str.indexOf(signAlignPos) >= 0) {
                         var a1 = arr[i].split(signAlignPos);
@@ -860,7 +996,7 @@ function beautify2(input, settings) {
             input = input.replace("@@alignall" + k, Array((align_groups_max[k] - align_groups[k] + 1)).join(" "));
         }
     }
-    if (settings.SignAlign) {
+    if (settings.SignAlignRegional) {
         for (var k = 0; k < align_i; k++) {
             input = input.replace("@@align" + k, Array((align_max[k] - align[k] + 2)).join(" "));
         }

VHDLFormatter.ts

@@ -60,23 +60,31 @@ declare global {
         regexLastIndexOf: (pattern: RegExp, startIndex: number) => number;
         reverse: () => string;
         regexStartsWith: (pattern: RegExp) => boolean;
+        count: (text: string) => number;
     }
 }
 
+String.prototype.count = function (text): number {
+    return this.split(text).length - 1;
+}
+
 String.prototype.regexStartsWith = function (pattern): boolean {
     var searchResult = this.search(pattern);
     return searchResult == 0;
 }
+
 String.prototype.regexIndexOf = function (pattern, startIndex) {
     startIndex = startIndex || 0;
     var searchResult = this.substr(startIndex).search(pattern);
     return (-1 === searchResult) ? -1 : searchResult + startIndex;
 }
+
 String.prototype.regexLastIndexOf = function (pattern, startIndex) {
     startIndex = startIndex === undefined ? this.length : startIndex;
     var searchResult = this.substr(0, startIndex).reverse().regexIndexOf(pattern, 0);
     return (-1 === searchResult) ? -1 : this.length - ++searchResult;
 }
+
 String.prototype.reverse = function () {
     return this.split('').reverse().join('');
 }
@@ -258,7 +266,7 @@ export class BeautifierSettings {
     RemoveComments: boolean;
     RemoveAsserts: boolean;
     CheckAlias: boolean;
-    SignAlign: boolean;
+    SignAlignRegional: boolean;
     SignAlignAll: boolean;
     KeywordCase: string;
     Indentation: string;
@@ -269,7 +277,7 @@ export class BeautifierSettings {
         this.RemoveComments = removeComments;
         this.RemoveAsserts = removeReport;
         this.CheckAlias = checkAlias;
-        this.SignAlign = signAlign;
+        this.SignAlignRegional = signAlign;
         this.SignAlignAll = signAlignAll;
         this.KeywordCase = keywordCase;
         this.Indentation = indentation;
@@ -308,7 +316,14 @@ export function beautify(input: string, settings: BeautifierSettings) {
     input = arr.join("\r\n");
     input = input.replace(/(PORT|PROCESS|GENERIC)[\s]*\(/g, '$1 (');
     input = SetNewLinesAfterSymbols(input, settings.NewLineSettings);
+    arr = input.split("\r\n");
+    let quotes = EscapeQuotes(arr);
+    if (settings.RemoveAsserts) {
+        RemoveAsserts(arr);//RemoveAsserts must be after EscapeQuotes
+    }
 
+    ApplyNoNewLineAfter(arr, settings.NewLineSettings.noNewLineAfter);
+    input = arr.join("\r\n");
     //input = beautify2(input, settings);
 
     //new
@@ -321,8 +336,9 @@ export function beautify(input: string, settings: BeautifierSettings) {
     input = input.replace(/([\(\)])[ ]?(THEN)/gi, '$1 $2');
     input = input.replace(/(^|[\(\)])[ ]?(AND|OR|XOR|XNOR)[ ]*([\(])/g, '$1 $2 $3');
     input = input.replace(/ ([\-\*\/=+<>])[ ]*([\-\*\/=+<>]) /g, " $1$2 ");
-    input = input.replace(/\r\n[ \t]+--\r\n/g, "\r\n");
+    //input = input.replace(/\r\n[ \t]+--\r\n/g, "\r\n");
     input = input.replace(/[ ]+/g, ' ');
+    input = input.replace(/[ \t]+\r\n/g, "\r\n");
     input = input.replace(/\r\n\r\n\r\n/g, '\r\n');
     input = input.replace(/[\r\n\s]+$/g, '');
     input = input.replace(/[ \t]+\)/g, ')');
@@ -332,6 +348,10 @@ export function beautify(input: string, settings: BeautifierSettings) {
     arr = FormattedLineToString(result, settings.Indentation);
     input = arr.join("\r\n");
 
+    for (var k = 0; k < quotes.length; k++) {
+        input = input.replace(ILQuotesPrefix + k, quotes[k]);
+    }
+
     for (var k = 0; k < commentsIndex; k++) {
         input = input.replace(ILCommentPrefix + k, comments[k]);
     }
@@ -357,7 +377,12 @@ export function FormattedLineToString(arr: (FormattedLine | FormattedLine[])[],
     }
     arr.forEach(i => {
         if (i instanceof FormattedLine) {
-            result.push((Array(i.Indent + 1).join(indentation)) + i.Line);
+            if (i.Line.length > 0) {
+                result.push((Array(i.Indent + 1).join(indentation)) + i.Line);
+            }
+            else {
+                result.push("");
+            }
         }
         else {
             result = result.concat(FormattedLineToString(i, indentation));
@@ -366,8 +391,115 @@ export function FormattedLineToString(arr: (FormattedLine | FormattedLine[])[],
     return result;
 }
 
-export function beautifyCaseBlock(inputs: Array<string>, result: (FormattedLine | FormattedLine[])[], settings: BeautifierSettings, startIndex: number, indent: number, isFirstKeyWord?: boolean): number {
-    if (!inputs[startIndex].regexStartsWith(/(CASE)([\s]|$)/)) {
+function GetCloseparentheseEndIndex(inputs: Array<string>, startIndex: number): number {
+    let openParentheseCount: number = 0;
+    let closeParentheseCount: number = 0;
+    for (let i = startIndex; i < inputs.length; i++) {
+        let input = inputs[i];
+        openParentheseCount += input.count("(");
+        closeParentheseCount += input.count(")");
+        if (openParentheseCount > 0
+            && openParentheseCount <= closeParentheseCount) {
+            return i;
+        }
+    }
+    return startIndex;
+}
+
+export function beautifyPortGenericBlock(inputs: Array<string>, result: (FormattedLine | FormattedLine[])[], settings: BeautifierSettings, startIndex: number, indent: number, mode: string): number {
+    let firstLine: string = inputs[startIndex];
+    let regex: RegExp = new RegExp("[\\w\\s:]*(" + mode + ")([\\s]|$)");
+    if (!firstLine.regexStartsWith(regex)) {
+        return startIndex;
+    }
+    let firstLineHasParenthese: boolean = firstLine.indexOf("(") >= 0;
+    let hasParenthese: boolean = firstLineHasParenthese;
+    let blockBodyStartIndex = startIndex;
+    let secondLineHasParenthese: boolean = inputs[startIndex + 1].startsWith("(");
+    if (secondLineHasParenthese) {
+        hasParenthese = true;
+        blockBodyStartIndex++;
+    }
+    let endIndex: number = hasParenthese ? GetCloseparentheseEndIndex(inputs, startIndex) : startIndex;
+    if (endIndex != startIndex && firstLineHasParenthese) {
+        inputs[startIndex] = inputs[startIndex].replace(/(PORT|GENERIC|PROCEDURE)([\w ]+)\(([\w\(\) ]+)/, '$1$2(\r\n$3');
+        let newInputs = inputs[startIndex].split("\r\n");
+        if (newInputs.length == 2) {
+            inputs[startIndex] = newInputs[0];
+            inputs.splice(startIndex + 1, 0, newInputs[1]);
+            endIndex++;
+        }
+    }
+    else if (endIndex != startIndex && secondLineHasParenthese) {
+        inputs[startIndex + 1] = inputs[startIndex + 1].replace(/\(([\w\(\) ]+)/, '(\r\n$1');
+        let newInputs = inputs[startIndex + 1].split("\r\n");
+        if (newInputs.length == 2) {
+            inputs[startIndex + 1] = newInputs[0];
+            inputs.splice(startIndex + 2, 0, newInputs[1]);
+            endIndex++;
+        }
+    }
+    if (firstLineHasParenthese && inputs[startIndex].indexOf("MAP") > 0) {
+        inputs[startIndex] = inputs[startIndex].replace(/([^\w])(MAP)\s+\(/g, '$1$2(');
+    }
+    result.push(new FormattedLine(inputs[startIndex], indent));
+    if (secondLineHasParenthese) {
+        result.push(new FormattedLine(inputs[startIndex + 1], indent));
+    }
+    let blockBodyEndIndex = endIndex;
+    let i = beautify3(inputs, result, settings, blockBodyStartIndex + 1, indent + 1, endIndex);
+    if (inputs[i].startsWith(")")) {
+        (<FormattedLine>result[i]).Indent--;
+        blockBodyEndIndex--;
+    }
+    if (settings.SignAlignRegional) {
+        blockBodyStartIndex++;
+        SignAlignRegional(result, blockBodyStartIndex, blockBodyEndIndex);
+    }
+    return i;
+}
+
+export function SignAlignRegional(result: (FormattedLine | FormattedLine[])[], startIndex: number, endIndex: number) {
+    let maxSymbolIndex = {};
+    let allSymbolIndex = {};
+    for (let i = startIndex; i <= endIndex; i++) {
+        let line = (<FormattedLine>result[i]).Line;
+        SetSymbolIndices(line, ":", maxSymbolIndex, allSymbolIndex, i);
+        SetSymbolIndices(line, ":=", maxSymbolIndex, allSymbolIndex, i);
+        SetSymbolIndices(line, "=>", maxSymbolIndex, allSymbolIndex, i);
+    }
+    for (let key in maxSymbolIndex) {
+        let maxIndex = maxSymbolIndex[key];
+        for (let lineIndex in allSymbolIndex[key]) {
+            let symbolIndex = allSymbolIndex[key][lineIndex];
+            if (symbolIndex == maxIndex) {
+                continue;
+            }
+            let line = (<FormattedLine>result[lineIndex]).Line;
+            (<FormattedLine>result[lineIndex]).Line = line.substring(0, symbolIndex)
+                + (Array(maxIndex - symbolIndex + 1).join(" "))
+                + line.substring(symbolIndex);
+        }
+    }
+}
+
+function SetSymbolIndices(line: string, symbol: string, maxSymbolIndex: {}, allSymbolIndex: {}, index: number) {
+    let regex: RegExp = new RegExp("([\\s\\w]|^)" + symbol + "([\\s\\w]|$)");
+    let colonIndex = line.regexIndexOf(regex);
+    if (colonIndex > 0) {
+        if (maxSymbolIndex.hasOwnProperty(symbol)) {
+            maxSymbolIndex[symbol] = Math.max(maxSymbolIndex[symbol], colonIndex);
+        }
+        else {
+            maxSymbolIndex[symbol] = colonIndex;
+            allSymbolIndex[symbol] = {};
+        }
+        allSymbolIndex[symbol][index] = colonIndex;
+    }
+}
+
+export function beautifyCaseBlock(inputs: Array<string>, result: (FormattedLine | FormattedLine[])[], settings: BeautifierSettings, startIndex: number, indent: number): number {
+    if (!inputs[startIndex].regexStartsWith(/(.+:\s*)?(CASE)([\s]|$)/)) {
         return startIndex;
     }
     result.push(new FormattedLine(inputs[startIndex], indent));
@@ -377,9 +509,9 @@ export function beautifyCaseBlock(inputs: Array<string>, result: (FormattedLine
     return i;
 }
 
-export function beautify3(inputs: Array<string>, result: (FormattedLine | FormattedLine[])[], settings: BeautifierSettings, startIndex: number, indent: number, isFirstKeyWord?: boolean): number {
+export function beautify3(inputs: Array<string>, result: (FormattedLine | FormattedLine[])[], settings: BeautifierSettings, startIndex: number, indent: number, endIndex?: number): number {
     let i: number;
-    let regexOneLineBlockKeyWords: RegExp = new RegExp(/(PROCEDURE|FUNCTION|IMPURE FUNCTION)[^\w_](?!.+[^\w_]IS([^\w_]|$))/);//match PROCEDURE..; but not PROCEDURE .. IS;
+    let regexOneLineBlockKeyWords: RegExp = new RegExp(/(PROCEDURE|FUNCTION|IMPURE FUNCTION)[^\w](?!.+[^\w]IS([^\w]|$))/);//match PROCEDURE..; but not PROCEDURE .. IS;
     let blockMidKeyWords: Array<string> = ["ELSE", "ELSIF", "WHEN", "BEGIN"];
     let blockStartsKeyWords: Array<string> = [
         "IF",
@@ -389,25 +521,37 @@ export function beautify3(inputs: Array<string>, result: (FormattedLine | Format
         "PACKAGE",
         "PROCESS",
         "POSTPONED PROCESS",
-        "(\\w+:\\s+PROCESS)",
+        "([\\w\\s]+:\\s*PROCESS)",
         "FUNCTION",
         "IMPURE FUNCTION",
         "(.+\\sPROTECTED)",
-        "COMPONENT"];
+        "COMPONENT",
+        "ENTITY"];
     let blockEndsKeyWords: Array<string> = ["END"];
 
     let newLineAfterKeyWordsStr: string = blockStartsKeyWords.join("|");
     let blockEndKeyWordsStr: string = blockEndsKeyWords.join("|");
     let blockMidKeyWordsStr: string = blockMidKeyWords.join("|");
-    let regexBlockMidKeyWords: RegExp = new RegExp("(" + blockMidKeyWordsStr + ")([^\\w_]|$)")
-    let regexBlockStartsKeywords: RegExp = new RegExp("(" + newLineAfterKeyWordsStr + ")([^\\w_]|$)")
-    let regexBlockEndsKeyWords: RegExp = new RegExp("(" + blockEndKeyWordsStr + ")([^\\w_]|$)")
-    for (i = startIndex; i < inputs.length; i++) {
+    let regexBlockMidKeyWords: RegExp = new RegExp("(" + blockMidKeyWordsStr + ")([^\\w]|$)")
+    let regexBlockStartsKeywords: RegExp = new RegExp("(" + newLineAfterKeyWordsStr + ")([^\\w]|$)")
+    let regexBlockEndsKeyWords: RegExp = new RegExp("(" + blockEndKeyWordsStr + ")([^\\w]|$)")
+    if (endIndex == null) {
+        endIndex = inputs.length - 1;
+    }
+    for (i = startIndex; i <= endIndex; i++) {
         let input: string = inputs[i].trim();
-        if (input.regexStartsWith(/(CASE)([\s]|$)/)) {
+        if (input.regexStartsWith(/(.+:\s*)?(CASE)([\s]|$)/)) {
             i = beautifyCaseBlock(inputs, result, settings, i, indent);
             continue;
         }
+        if (input.regexStartsWith(/[\w\s:]*PORT([\s]|$)/)) {
+            i = beautifyPortGenericBlock(inputs, result, settings, i, indent, "PORT");
+            continue;
+        }
+        if (input.regexStartsWith(/[\w\s:]*GENERIC([\s]|$)/)) {
+            i = beautifyPortGenericBlock(inputs, result, settings, i, indent, "GENERIC");
+            continue;
+        }
         result.push(new FormattedLine(input, indent));
         if (startIndex != 0
             && (input.regexStartsWith(regexBlockMidKeyWords))) {
@@ -768,7 +912,7 @@ function beautify2(input, settings: BeautifierSettings): string {
                 if (currentSign == alignedSigns.length) {
                     lastAlignedSign = "";
                 }
-            } else if (settings.SignAlign) {
+            } else if (settings.SignAlignRegional) {
                 if (port_b && signAlignPos != "") {
                     if (str.indexOf(signAlignPos) >= 0) {
                         var a1 = arr[i].split(signAlignPos);
@@ -911,7 +1055,7 @@ function beautify2(input, settings: BeautifierSettings): string {
         }
     }
 
-    if (settings.SignAlign) {
+    if (settings.SignAlignRegional) {
         for (var k = 0; k < align_i; k++) {
             input = input.replace("@@align" + k, Array((align_max[k] - align[k] + 2)).join(" "));
         }

VHDLFormatterUnitTests.js

@@ -316,7 +316,7 @@ function Beautify3Case11() {
         new VHDLFormatter_9.FormattedLine("END PROCEDURE;", 1),
         new VHDLFormatter_9.FormattedLine("END PACKAGE BODY;", 0)
     ];
-    UnitTest6(VHDLFormatter_8.beautify3, "package", settings, inputs, expected, 0, expected.length - 1, 0);
+    UnitTest6(VHDLFormatter_8.beautify3, "package procedure", settings, inputs, expected, 0, expected.length - 1, 0);
 }
 function Beautify3Case12() {
     let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
@@ -367,7 +367,7 @@ function Beautify3Case12() {
         new VHDLFormatter_9.FormattedLine("POSTPONED assert x = 1;", 1),
         new VHDLFormatter_9.FormattedLine("END ARCHITECTURE;", 0)
     ];
-    UnitTest6(VHDLFormatter_8.beautify3, "package", settings, inputs, expected, 0, expected.length - 1, 0);
+    UnitTest6(VHDLFormatter_8.beautify3, "package postponed procedure", settings, inputs, expected, 0, expected.length - 1, 0);
 }
 function Beautify3Case13() {
     let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
@@ -513,7 +513,7 @@ function compareFormattedLine(expected, actual, message, cumulateTestCount) {
 function assert(testName, expected, actual, message) {
     var result = CompareString(actual, expected);
     if (result != true) {
-        console.log(testName + " failed: " + result);
+        console.log(testName + " failed: \n" + result);
     }
     else {
         //console.log(testName + " pass");
@@ -592,12 +592,8 @@ function UnitTest() {
     expected = "ENTITY TB_DISPLAY IS\r\n    -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n    -- signal declarations\r\nBEGIN\r\n    -- component instance(s)\r\nEND TEST;";
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("ENTITY ARCHITECTURE", expected, actual);
-    newSettings = deepCopy(settings);
-    newSettings.SignAlign = true;
-    input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
-    expected = "PORT MAP(\r\n    input_1  => input_1_sig, \r\n    input_2  => input_2_sig, \r\n    output   => output_sig\r\n);";
-    actual = VHDLFormatter_1.beautify(input, newSettings);
-    assert("Sign align in PORT", expected, actual);
+    IntegrationTest5();
+    IntegrationTest6();
     input = 'if a(3 downto 0) > "0100" then\r\na(3 downto 0) := a(3 downto 0) + "0011" ;\r\nend if ;';
     expected = 'IF a(3 DOWNTO 0) > "0100" THEN\r\n    a(3 DOWNTO 0) := a(3 DOWNTO 0) + "0011";\r\nEND IF;';
     actual = VHDLFormatter_1.beautify(input, settings);
@@ -606,56 +602,78 @@ function UnitTest() {
     expected = "IF s = '1' THEN\r\n    o <= \"010\";\r\nELSE\r\n    o <= \"101\";\r\nEND IF;";
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("IF ELSE END IF case 1", expected, actual);
+    newSettings = deepCopy(settings);
+    newSettings.NewLineSettings.newLineAfter.push("ELSE");
     input = "IF (s = r) THEN rr := '0'; ELSE rr := '1'; END IF;";
     expected = "IF (s = r) THEN\r\n    rr := '0';\r\nELSE\r\n    rr := '1';\r\nEND IF;";
-    actual = VHDLFormatter_1.beautify(input, settings);
+    actual = VHDLFormatter_1.beautify(input, newSettings);
     assert("IF ELSE END IF case 2", expected, actual);
     input = 'P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n  C1: case x is\r\n      when 1 => Out_1 <= 0;\r\n      when 2 => Out_1 <= 1;\r\n  end case C1;\r\n  C2: case y is\r\n      when "00" => Out_2 <= 0;\r\n      when "01" => Out_2 <= 1;\r\n  end case C2;\r\nend process;';
     expected = 'P1 : PROCESS\r\n    VARIABLE x : INTEGER RANGE 1 TO 3;\r\n    VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n    C1 : CASE x IS\r\n        WHEN 1 => Out_1 <= 0;\r\n        WHEN 2 => Out_1 <= 1;\r\n    END CASE C1;\r\n    C2 : CASE y IS\r\n        WHEN "00" => Out_2 <= 0;\r\n        WHEN "01" => Out_2 <= 1;\r\n    END CASE C2;\r\nEND PROCESS;';
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("WHEN CASE", expected, actual);
     input = "case READ_CPU_STATE is\r\n  when WAITING =>\r\n    if CPU_DATA_VALID = '1' then\r\n      CPU_DATA_READ  <= '1';\r\n      READ_CPU_STATE <= DATA1;\r\n    end if;\r\n  when DATA1 =>\r\n    -- etc.\r\nend case;";
-    expected = "CASE READ_CPU_STATE IS\r\n    WHEN WAITING => \r\n        IF CPU_DATA_VALID = '1' THEN\r\n            CPU_DATA_READ <= '1';\r\n            READ_CPU_STATE <= DATA1;\r\n        END IF;\r\n    WHEN DATA1 => \r\n        -- etc.\r\nEND CASE;";
+    expected = "CASE READ_CPU_STATE IS\r\n    WHEN WAITING =>\r\n        IF CPU_DATA_VALID = '1' THEN\r\n            CPU_DATA_READ <= '1';\r\n            READ_CPU_STATE <= DATA1;\r\n        END IF;\r\n    WHEN DATA1 =>\r\n        -- etc.\r\nEND CASE;";
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("WHEN CASE & IF", expected, actual);
     input = "entity aa is\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\nend aa;\r\narchitecture bb of aa is\r\n   component cc\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    end cc;\r\n\r\nbegin\r\n  C : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\nend;";
-    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\nEND;";
+    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\nEND;";
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("PORT MAP", expected, actual);
     input = "entity aa is\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\nend aa;\r\narchitecture bb of aa is\r\n   component cc\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    end cc;\r\n\r\nbegin\r\n  C : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\n  D : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\nend;";
-    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\n    D : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\nEND;";
+    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\n    D : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\nEND;";
     actual = VHDLFormatter_1.beautify(input, settings);
     assert("Multiple PORT MAPs", expected, actual);
     input = "port (a : in std_logic;\r\n b : in std_logic;\r\n);";
-    expected = "PORT \r\n(\r\n    a : IN std_logic;\r\n    b : IN std_logic;\r\n);";
+    expected = "PORT\r\n(\r\n    a : IN std_logic;\r\n    b : IN std_logic;\r\n);";
     new_line_after_symbols_2 = new VHDLFormatter_3.NewLineSettings();
     new_line_after_symbols_2.newLineAfter = ["then", ";", "generic", "port"];
     newSettings = deepCopy(settings);
     newSettings.NewLineSettings = new_line_after_symbols_2;
     actual = VHDLFormatter_1.beautify(input, newSettings);
     assert("New line after PORT", expected, actual);
+    newSettings = deepCopy(settings);
+    newSettings.NewLineSettings.newLineAfter = [];
     input = "component a is\r\nport( Data : inout Std_Logic_Vector(7 downto 0););\r\nend component a;";
     expected = "COMPONENT a IS\r\n    PORT (Data : INOUT Std_Logic_Vector(7 DOWNTO 0););\r\nEND COMPONENT a;";
     actual = VHDLFormatter_1.beautify(input, newSettings);
-    assert("New line aster PORT (single line)", expected, actual);
+    assert("New line after PORT (single line)", expected, actual);
     input = "process xyx (vf,fr,\r\nde -- comment\r\n)";
     expected = "PROCESS xyx (vf, fr, \r\n             de -- comment\r\n             )";
     actual = VHDLFormatter_1.beautify(input, newSettings);
     assert("Align parameters in PROCESS", expected, actual);
     input = "architecture a of b is\r\nbegin\r\n    process (w)\r\n    variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n    a := (others => '0') ;\r\nend process ;\r\nend a;";
-    expected = "ARCHITECTURE a OF b IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n    BEGIN\r\n        a := (OTHERS => '0');\r\n    END PROCESS;\r\nEND a;";
+    expected = "ARCHITECTURE a OF b IS\r\nBEGIN\r\n    PROCESS (w)\r\n        VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n    BEGIN\r\n        a := (OTHERS => '0');\r\n    END PROCESS;\r\nEND a;";
     actual = VHDLFormatter_1.beautify(input, newSettings);
     assert("Double BEGIN", expected, actual);
     let newSettings2 = deepCopy(newSettings);
     newSettings2.SignAlignAll = true;
     input = "entity a is\r\n    port ( w  : in  std_logic_vector (7 downto 0) ;\r\n           w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n    process ( w )\r\n    variable t : std_logic_vector (4 downto 0) ;\r\n    variable bcd     : std_logic_vector (11 downto 0) ;\r\nbegin\r\n    b(2 downto 0) := w(7 downto 5) ;\r\n    t         := w(4 downto 0) ;\r\n    w_s <= b(11 downto 8) ;\r\n    w <= b(3  downto 0) ;\r\nend process ;\r\nend b ;";
-    expected = "ENTITY a IS\r\n    PORT \r\n    (\r\n        w   : IN std_logic_vector (7 DOWNTO 0);\r\n        w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t   : std_logic_vector (4 DOWNTO 0);\r\n    VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
+    expected = "ENTITY a IS\r\n    PORT\r\n    (\r\n        w   : IN std_logic_vector (7 DOWNTO 0);\r\n        w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t   : std_logic_vector (4 DOWNTO 0);\r\n    VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
     actual = VHDLFormatter_1.beautify(input, newSettings2);
     assert("Align signs in all places", expected, actual);
-    input = "begin\r\n  P0 : process(input)\r\n  variable value: Integer;\r\n  begin\r\n    result(i) := '0';\r\n  end process P0;\r\nend behavior;";
-    expected = "BEGIN\r\n    P0 : PROCESS (input)\r\n        VARIABLE value : INTEGER;\r\n    BEGIN\r\n        result(i) := '0';\r\n    END PROCESS P0;\r\nEND behavior;";
-    actual = VHDLFormatter_1.beautify(input, newSettings);
-    assert("Indent after Begin", expected, actual);
+}
+function IntegrationTest5() {
+    let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
+    new_line_after_symbols.newLineAfter = ["then", ";"];
+    new_line_after_symbols.noNewLineAfter = ["generic"];
+    let settings = new VHDLFormatter_4.BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
+    settings.SignAlignRegional = true;
+    let input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
+    let expected = "PORT MAP(\r\n    input_1 => input_1_sig,\r\n    input_2 => input_2_sig,\r\n    output  => output_sig\r\n);";
+    let actual = VHDLFormatter_1.beautify(input, settings);
+    assert("Sign align in PORT", expected, actual);
+}
+function IntegrationTest6() {
+    let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
+    new_line_after_symbols.newLineAfter = ["then", ";", "port map"];
+    new_line_after_symbols.noNewLineAfter = ["generic"];
+    let settings = new VHDLFormatter_4.BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
+    settings.SignAlignRegional = true;
+    let input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
+    let expected = "PORT MAP\r\n(\r\n    input_1 => input_1_sig,\r\n    input_2 => input_2_sig,\r\n    output  => output_sig\r\n);";
+    let actual = VHDLFormatter_1.beautify(input, settings);
+    assert("Sign align in PORT & new line after MAP", expected, actual);
 }
 function IntegrationTest2() {
     let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
@@ -664,7 +682,7 @@ function IntegrationTest2() {
     let settings = new VHDLFormatter_4.BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
     settings.RemoveComments = true;
     let input = "architecture TB of TB_CPU is\r\n    component CPU_IF\r\n    port   -- port list\r\n    end component;\r\n    signal CPU_DATA_VALID: std_ulogic;\r\n    signal CLK, RESET: std_ulogic := '0';\r\n    constant PERIOD : time := 10 ns;\r\n    constant MAX_SIM: time := 50 * PERIOD;\r\n    begin\r\n    -- concurrent statements\r\n    end TB;";
-    let expected = "ARCHITECTURE TB OF TB_CPU IS\r\n    COMPONENT CPU_IF\r\n        PORT \r\n    END COMPONENT;\r\n    SIGNAL CPU_DATA_VALID : std_ulogic;\r\n    SIGNAL CLK, RESET : std_ulogic := '0';\r\n    CONSTANT PERIOD : TIME := 10 ns;\r\n    CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
+    let expected = "ARCHITECTURE TB OF TB_CPU IS\r\n    COMPONENT CPU_IF\r\n        PORT\r\n    END COMPONENT;\r\n    SIGNAL CPU_DATA_VALID : std_ulogic;\r\n    SIGNAL CLK, RESET : std_ulogic := '0';\r\n    CONSTANT PERIOD : TIME := 10 ns;\r\n    CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
     let actual = VHDLFormatter_1.beautify(input, settings);
     assert("Remove comments", expected, actual);
 }

VHDLFormatterUnitTests.ts

@@ -333,7 +333,7 @@ function Beautify3Case11() {
         new FormattedLine("END PROCEDURE;", 1),
         new FormattedLine("END PACKAGE BODY;", 0)
     ];
-    UnitTest6(beautify3, "package", settings, inputs, expected, 0, expected.length - 1, 0);
+    UnitTest6(beautify3, "package procedure", settings, inputs, expected, 0, expected.length - 1, 0);
 }
 
 function Beautify3Case12() {
@@ -385,7 +385,7 @@ function Beautify3Case12() {
         new FormattedLine("POSTPONED assert x = 1;", 1),
         new FormattedLine("END ARCHITECTURE;", 0)
     ];
-    UnitTest6(beautify3, "package", settings, inputs, expected, 0, expected.length - 1, 0);
+    UnitTest6(beautify3, "package postponed procedure", settings, inputs, expected, 0, expected.length - 1, 0);
 }
 
 function Beautify3Case13() {
@@ -544,7 +544,7 @@ function compareFormattedLine(expected: FormattedLine, actual: FormattedLine, me
 function assert(testName, expected: string, actual: string, message?) {
     var result = CompareString(actual, expected);
     if (result != true) {
-        console.log(testName + " failed: " + result);
+        console.log(testName + " failed: \n" + result);
     }
     else {
         //console.log(testName + " pass");
@@ -649,12 +649,8 @@ function UnitTest() {
     actual = beautify(input, settings);
     assert("ENTITY ARCHITECTURE", expected, actual);
 
-    newSettings = deepCopy(settings);
-    newSettings.SignAlign = true;
-    input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
-    expected = "PORT MAP(\r\n    input_1  => input_1_sig, \r\n    input_2  => input_2_sig, \r\n    output   => output_sig\r\n);";
-    actual = beautify(input, newSettings);
-    assert("Sign align in PORT", expected, actual);
+    IntegrationTest5();
+    IntegrationTest6();
 
     input = 'if a(3 downto 0) > "0100" then\r\na(3 downto 0) := a(3 downto 0) + "0011" ;\r\nend if ;';
     expected = 'IF a(3 DOWNTO 0) > "0100" THEN\r\n    a(3 DOWNTO 0) := a(3 DOWNTO 0) + "0011";\r\nEND IF;';
@@ -666,9 +662,11 @@ function UnitTest() {
     actual = beautify(input, settings);
     assert("IF ELSE END IF case 1", expected, actual);
 
+    newSettings = deepCopy(settings);
+    newSettings.NewLineSettings.newLineAfter.push("ELSE");
     input = "IF (s = r) THEN rr := '0'; ELSE rr := '1'; END IF;";
     expected = "IF (s = r) THEN\r\n    rr := '0';\r\nELSE\r\n    rr := '1';\r\nEND IF;";
-    actual = beautify(input, settings);
+    actual = beautify(input, newSettings);
     assert("IF ELSE END IF case 2", expected, actual);
 
     input = 'P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n  C1: case x is\r\n      when 1 => Out_1 <= 0;\r\n      when 2 => Out_1 <= 1;\r\n  end case C1;\r\n  C2: case y is\r\n      when "00" => Out_2 <= 0;\r\n      when "01" => Out_2 <= 1;\r\n  end case C2;\r\nend process;';
@@ -677,22 +675,22 @@ function UnitTest() {
     assert("WHEN CASE", expected, actual);
 
     input = "case READ_CPU_STATE is\r\n  when WAITING =>\r\n    if CPU_DATA_VALID = '1' then\r\n      CPU_DATA_READ  <= '1';\r\n      READ_CPU_STATE <= DATA1;\r\n    end if;\r\n  when DATA1 =>\r\n    -- etc.\r\nend case;";
-    expected = "CASE READ_CPU_STATE IS\r\n    WHEN WAITING => \r\n        IF CPU_DATA_VALID = '1' THEN\r\n            CPU_DATA_READ <= '1';\r\n            READ_CPU_STATE <= DATA1;\r\n        END IF;\r\n    WHEN DATA1 => \r\n        -- etc.\r\nEND CASE;";
+    expected = "CASE READ_CPU_STATE IS\r\n    WHEN WAITING =>\r\n        IF CPU_DATA_VALID = '1' THEN\r\n            CPU_DATA_READ <= '1';\r\n            READ_CPU_STATE <= DATA1;\r\n        END IF;\r\n    WHEN DATA1 =>\r\n        -- etc.\r\nEND CASE;";
     actual = beautify(input, settings);
     assert("WHEN CASE & IF", expected, actual);
 
     input = "entity aa is\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\nend aa;\r\narchitecture bb of aa is\r\n   component cc\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    end cc;\r\n\r\nbegin\r\n  C : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\nend;";
-    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\nEND;";
+    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\nEND;";
     actual = beautify(input, settings);
     assert("PORT MAP", expected, actual);
 
     input = "entity aa is\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\n    port (a : in std_logic;\r\n          b : in std_logic;\r\n         );\r\nend aa;\r\narchitecture bb of aa is\r\n   component cc\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    port(\r\n         a : in std_logic;\r\n         b : in std_logic;\r\n        );\r\n    end cc;\r\n\r\nbegin\r\n  C : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\n  D : cc port map (\r\n          long => a,\r\n          b => b\r\n        );\r\nend;";
-    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\n    D : cc\r\n    PORT MAP(\r\n        long => a, \r\n        b => b\r\n    );\r\nEND;";
+    expected = "ENTITY aa IS\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\n    PORT (\r\n        a : IN std_logic;\r\n        b : IN std_logic;\r\n    );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n    COMPONENT cc\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n        PORT (\r\n            a : IN std_logic;\r\n            b : IN std_logic;\r\n        );\r\n    END cc;\r\n\r\nBEGIN\r\n    C : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\n    D : cc PORT MAP(\r\n        long => a,\r\n        b => b\r\n    );\r\nEND;";
     actual = beautify(input, settings);
     assert("Multiple PORT MAPs", expected, actual);
 
     input = "port (a : in std_logic;\r\n b : in std_logic;\r\n);";
-    expected = "PORT \r\n(\r\n    a : IN std_logic;\r\n    b : IN std_logic;\r\n);";
+    expected = "PORT\r\n(\r\n    a : IN std_logic;\r\n    b : IN std_logic;\r\n);";
     new_line_after_symbols_2 = new NewLineSettings();
     new_line_after_symbols_2.newLineAfter = ["then", ";", "generic", "port"];
     newSettings = deepCopy(settings);
@@ -700,10 +698,12 @@ function UnitTest() {
     actual = beautify(input, newSettings);
     assert("New line after PORT", expected, actual);
 
+    newSettings = deepCopy(settings);
+    newSettings.NewLineSettings.newLineAfter = [];
     input = "component a is\r\nport( Data : inout Std_Logic_Vector(7 downto 0););\r\nend component a;";
     expected = "COMPONENT a IS\r\n    PORT (Data : INOUT Std_Logic_Vector(7 DOWNTO 0););\r\nEND COMPONENT a;";
     actual = beautify(input, newSettings);
-    assert("New line aster PORT (single line)", expected, actual);
+    assert("New line after PORT (single line)", expected, actual);
 
     input = "process xyx (vf,fr,\r\nde -- comment\r\n)";
     expected = "PROCESS xyx (vf, fr, \r\n             de -- comment\r\n             )";
@@ -711,21 +711,40 @@ function UnitTest() {
     assert("Align parameters in PROCESS", expected, actual);
 
     input = "architecture a of b is\r\nbegin\r\n    process (w)\r\n    variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n    a := (others => '0') ;\r\nend process ;\r\nend a;";
-    expected = "ARCHITECTURE a OF b IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n    BEGIN\r\n        a := (OTHERS => '0');\r\n    END PROCESS;\r\nEND a;";
+    expected = "ARCHITECTURE a OF b IS\r\nBEGIN\r\n    PROCESS (w)\r\n        VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n    BEGIN\r\n        a := (OTHERS => '0');\r\n    END PROCESS;\r\nEND a;";
     actual = beautify(input, newSettings);
     assert("Double BEGIN", expected, actual);
 
     let newSettings2 = deepCopy(newSettings);
     newSettings2.SignAlignAll = true;
     input = "entity a is\r\n    port ( w  : in  std_logic_vector (7 downto 0) ;\r\n           w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n    process ( w )\r\n    variable t : std_logic_vector (4 downto 0) ;\r\n    variable bcd     : std_logic_vector (11 downto 0) ;\r\nbegin\r\n    b(2 downto 0) := w(7 downto 5) ;\r\n    t         := w(4 downto 0) ;\r\n    w_s <= b(11 downto 8) ;\r\n    w <= b(3  downto 0) ;\r\nend process ;\r\nend b ;";
-    expected = "ENTITY a IS\r\n    PORT \r\n    (\r\n        w   : IN std_logic_vector (7 DOWNTO 0);\r\n        w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t   : std_logic_vector (4 DOWNTO 0);\r\n    VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
+    expected = "ENTITY a IS\r\n    PORT\r\n    (\r\n        w   : IN std_logic_vector (7 DOWNTO 0);\r\n        w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n    );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n    PROCESS (w)\r\n    VARIABLE t   : std_logic_vector (4 DOWNTO 0);\r\n    VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n    BEGIN\r\n        b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n        t             := w(4 DOWNTO 0);\r\n        w_s <= b(11 DOWNTO 8);\r\n        w   <= b(3 DOWNTO 0);\r\n    END PROCESS;\r\nEND b;";
     actual = beautify(input, newSettings2);
     assert("Align signs in all places", expected, actual);
+}
 
-    input = "begin\r\n  P0 : process(input)\r\n  variable value: Integer;\r\n  begin\r\n    result(i) := '0';\r\n  end process P0;\r\nend behavior;";
-    expected = "BEGIN\r\n    P0 : PROCESS (input)\r\n        VARIABLE value : INTEGER;\r\n    BEGIN\r\n        result(i) := '0';\r\n    END PROCESS P0;\r\nEND behavior;";
-    actual = beautify(input, newSettings);
-    assert("Indent after Begin", expected, actual);
+function IntegrationTest5() {
+    let new_line_after_symbols: NewLineSettings = new NewLineSettings();
+    new_line_after_symbols.newLineAfter = ["then", ";"];
+    new_line_after_symbols.noNewLineAfter = ["generic"];
+    let settings: BeautifierSettings = new BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
+    settings.SignAlignRegional = true;
+    let input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
+    let expected = "PORT MAP(\r\n    input_1 => input_1_sig,\r\n    input_2 => input_2_sig,\r\n    output  => output_sig\r\n);";
+    let actual = beautify(input, settings);
+    assert("Sign align in PORT", expected, actual);
+}
+
+function IntegrationTest6() {
+    let new_line_after_symbols: NewLineSettings = new NewLineSettings();
+    new_line_after_symbols.newLineAfter = ["then", ";","port map"];
+    new_line_after_symbols.noNewLineAfter = ["generic"];
+    let settings: BeautifierSettings = new BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
+    settings.SignAlignRegional = true;
+    let input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
+    let expected = "PORT MAP\r\n(\r\n    input_1 => input_1_sig,\r\n    input_2 => input_2_sig,\r\n    output  => output_sig\r\n);";
+    let actual = beautify(input, settings);
+    assert("Sign align in PORT & new line after MAP", expected, actual);
 }
 
 function IntegrationTest2() {
@@ -735,7 +754,7 @@ function IntegrationTest2() {
     let settings: BeautifierSettings = new BeautifierSettings(false, false, false, false, false, "uppercase", "    ", new_line_after_symbols);
     settings.RemoveComments = true;
     let input = "architecture TB of TB_CPU is\r\n    component CPU_IF\r\n    port   -- port list\r\n    end component;\r\n    signal CPU_DATA_VALID: std_ulogic;\r\n    signal CLK, RESET: std_ulogic := '0';\r\n    constant PERIOD : time := 10 ns;\r\n    constant MAX_SIM: time := 50 * PERIOD;\r\n    begin\r\n    -- concurrent statements\r\n    end TB;"
-    let expected = "ARCHITECTURE TB OF TB_CPU IS\r\n    COMPONENT CPU_IF\r\n        PORT \r\n    END COMPONENT;\r\n    SIGNAL CPU_DATA_VALID : std_ulogic;\r\n    SIGNAL CLK, RESET : std_ulogic := '0';\r\n    CONSTANT PERIOD : TIME := 10 ns;\r\n    CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
+    let expected = "ARCHITECTURE TB OF TB_CPU IS\r\n    COMPONENT CPU_IF\r\n        PORT\r\n    END COMPONENT;\r\n    SIGNAL CPU_DATA_VALID : std_ulogic;\r\n    SIGNAL CLK, RESET : std_ulogic := '0';\r\n    CONSTANT PERIOD : TIME := 10 ns;\r\n    CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
     let actual = beautify(input, settings);
     assert("Remove comments", expected, actual);
 }