From 90077163938f7a6e0d29d7f2e27863333aa16fa8 Mon Sep 17 00:00:00 2001 From: g2384 Date: Sat, 1 May 2021 13:51:06 +0100 Subject: [PATCH] reset indent after port map --- VHDLFormatter.js | 8 +++ VHDLFormatter.ts | 8 +++ tests/VHDLFormatter.test.ts | 101 ++++++++++++++++++++++++++++++++ tests/VHDLFormatterUnitTests.ts | 19 ------ 4 files changed, 117 insertions(+), 19 deletions(-) diff --git a/VHDLFormatter.js b/VHDLFormatter.js index 6a530a0..b79cd6f 100644 --- a/VHDLFormatter.js +++ b/VHDLFormatter.js @@ -817,7 +817,15 @@ function beautify3(block, result, settings, indent) { continue; } if (input.regexStartsWith(/[\w\s:]*\bPORT\b([\s]|$)/)) { + var preCursor = block.cursor; beautifyPortGenericBlock(block, result, settings, indent, "PORT"); + var preLine = preCursor - 1; + if (preLine >= 0) { + var preL = block.lines[preLine]; + if (preL.regexIndexOf(/:\s+(COMPONENT|ENTITY)/) >= 0) { + indent--; + } + } continue; } if (input.regexStartsWith(/TYPE\s+\w+\s+IS\s+\(/)) { diff --git a/VHDLFormatter.ts b/VHDLFormatter.ts index 3dda213..d120fb5 100644 --- a/VHDLFormatter.ts +++ b/VHDLFormatter.ts @@ -899,7 +899,15 @@ export function beautify3(block: CodeBlock, result: (FormattedLine | FormattedLi continue; } if (input.regexStartsWith(/[\w\s:]*\bPORT\b([\s]|$)/)) { + var preCursor = block.cursor; beautifyPortGenericBlock(block, result, settings, indent, "PORT"); + var preLine = preCursor - 1; + if (preLine >= 0) { + var preL = block.lines[preLine]; + if (preL.regexIndexOf(/:\s+(COMPONENT|ENTITY)/) >= 0) { + indent--; + } + } continue; } if (input.regexStartsWith(/TYPE\s+\w+\s+IS\s+\(/)) { diff --git a/tests/VHDLFormatter.test.ts b/tests/VHDLFormatter.test.ts index 03fb466..aac8125 100644 --- a/tests/VHDLFormatter.test.ts +++ b/tests/VHDLFormatter.test.ts @@ -211,6 +211,107 @@ describe('VHDLFormatter', function () { let result = beautifyTestHelper(input, settings); expect(result).toStrictEqual(output); }) + + it('indent PORT map', function () { + let settings = GetDefaultSettings(); + settings.SignAlignSettings = new signAlignSettings(false, true, "", [], false); + let input = [ + "test_iobuf : component IOBUF", + "port map(", + " I => '0',", + " T => '0'", + ");", + "test_iobuf : component IOBUF", + " port map(", + " I => '0',", + " T => '0'", + ");" + ]; + let output = [ + "test_iobuf : COMPONENT IOBUF", + " PORT MAP(", + " I => '0',", + " T => '0'", + " );", + "test_iobuf : COMPONENT IOBUF", + " PORT MAP(", + " I => '0',", + " T => '0'", + " );" + ]; + let result = beautifyTestHelper(input, settings); + expect(result).toStrictEqual(output); + }) + + it('indent PORT map (2)', function () { + let settings = GetDefaultSettings(); + settings.SignAlignSettings = new signAlignSettings(false, true, "", [], false); + let input = [ + "i_Mux1 : entity work.T15_Mux(rtl) port map(", + " Sel => Sel,", + "Sig1 => Sig1,", + "Output => Output);", + "", + "-- Testbench process", + "process is", + "begin", + "wait for 10 ns;", + "Sel <= Sel + 1;", + "wait for 10 ns;", + "Sel <= \"UU\";", + "wait;", + "end process;" + ]; + let output = [ + "i_Mux1 : ENTITY work.T15_Mux(rtl) PORT MAP(", + " Sel => Sel,", + " Sig1 => Sig1,", + " Output => Output);", + "", + "-- Testbench process", + "PROCESS IS", + "BEGIN", + " WAIT FOR 10 ns;", + " Sel <= Sel + 1;", + " WAIT FOR 10 ns;", + " Sel <= \"UU\";", + " WAIT;", + "END PROCESS;" + ]; + let result = beautifyTestHelper(input, settings); + expect(result).toStrictEqual(output); + + }); + + it('multiline assignment', function () { + let settings = GetDefaultSettings(); + settings.SignAlignSettings = new signAlignSettings(false, true, "", [], false); + let input = [ + "test", + " := test" + ]; + let output = [ + "test", + " := test" // is this desired? + ]; + let result = beautifyTestHelper(input, settings); + expect(result).toStrictEqual(output); + }); + + it('align <= => signs', function () { + let settings = GetDefaultSettings(); + settings.SignAlignSettings = new signAlignSettings(false, true, "", [], false); + let input = [ + "a <= (b => '000'); -- test", + "looong <= (others => '0'); -- test" + ]; + let output = [ + "a <= (b => '000'); -- test", + "looong <= (OTHERS => '0'); -- test" // does comment need to be aligned? + ]; + let result = beautifyTestHelper(input, settings); + expect(result).toStrictEqual(output); + }); }); function beautifyTestHelper(array: Array, settings: BeautifierSettings): Array { diff --git a/tests/VHDLFormatterUnitTests.ts b/tests/VHDLFormatterUnitTests.ts index dd21b7a..ba5eb12 100644 --- a/tests/VHDLFormatterUnitTests.ts +++ b/tests/VHDLFormatterUnitTests.ts @@ -933,12 +933,10 @@ function IntegrationTest() { IntegrationTest67(); IntegrationTest68(); IntegrationTest69(); - IntegrationTest70(); IntegrationTest71(); IntegrationTest72(); IntegrationTest73(); IntegrationTest74(); - IntegrationTest76(); IntegrationTest77(); IntegrationTest78(); IntegrationTest79(); @@ -1318,14 +1316,6 @@ function IntegrationTest69() { assertAndCountTest("multiline enumerated type is", expected, actual); } -function IntegrationTest70() { - let settings = GetDefaultSettings(); - let input = 'test\r\n := test'; - let expected = 'test\r\n:= test'; - let actual = beautify(input, settings); - assertAndCountTest("multiline assignment", expected, actual); -} - function IntegrationTest71() { let settings = GetDefaultSettings(); let input = 'VARIABLE \\#$)!?\\ : INTEGER;\r\nVARIABLE \\try this in verilog\\ : BIT;\r\nVARIABLE \\Buffer\\ : BIT;'; @@ -1359,15 +1349,6 @@ function IntegrationTest74() { assertAndCountTest("end of line 2", expected, actual); } -function IntegrationTest76() { - let settings = GetDefaultSettings(); - settings.SignAlignSettings = new signAlignSettings(false, true, "", []); - let input = "a <= (b => '000'); -- test\r\nlooong <= (others => '0'); -- test"; - let expected = "a <= (b => '000'); -- test\r\nlooong <= (OTHERS => '0'); -- test"; - let actual = beautify(input, settings); - assertAndCountTest("align <= => signs", expected, actual); -} - function IntegrationTest77() { let settings = GetDefaultSettings(); let input = "WHEN -2;\r\nSIGNAL +0;";