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@ -6,6 +6,23 @@ VHDL formatter web online written in javascript |
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## Release Notes |
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## Release Notes |
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### 2.7 [2020-10-19] |
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- align concurrent signal assignment |
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- align in, out, buffer and inout key words |
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- fix single line PACKAGE indentation |
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- add more type names, support "STD_LOGIC", "STD_LOGIC_VECTOR", "STD_ULOGIC", "STD_ULOGIC_VECTOR" |
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- add new lines at the end of file |
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- update packages |
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### 2.6 [2020-02-23] |
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- support VHDL-2008 block comment /* */ |
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- use jest |
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- indent multi-line signal and constant declarations |
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- do not add space between "<" or ">"; e.g. "<<<" will become " <<< " and not " < < < " |
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- array type definition breaks when formatting; e.g. "RANGE <>" becomes "RANGE < >" |
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### 2.5 [2019-03-13] |
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### 2.5 [2019-03-13] |
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- keep the front page concise |
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- keep the front page concise |
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