letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;";
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;";
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
expected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT \r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
expected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT \r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
input="entity TB_DISPLAY is\r\n-- port declarations\r\nend TB_DISPLAY;\r\n\r\narchitecture TEST of TB_DISPLAY is\r\n-- signal declarations\r\nbegin\r\n-- component instance(s)\r\nend TEST;";
input="entity TB_DISPLAY is\r\n-- port declarations\r\nend TB_DISPLAY;\r\n\r\narchitecture TEST of TB_DISPLAY is\r\n-- signal declarations\r\nbegin\r\n-- component instance(s)\r\nend TEST;";
expected="ENTITY TB_DISPLAY IS\r\n -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n -- signal declarations\r\nBEGIN\r\n -- component instance(s)\r\nEND TEST;";
expected="ENTITY TB_DISPLAY IS\r\n -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n -- signal declarations\r\nBEGIN\r\n -- component instance(s)\r\nEND TEST;";
console.log("IF ELSE END IF case 2",actual==expected);
assert("IF ELSE END IF case 2",expected,actual);
input='P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n C1: case x is\r\n when 1 => Out_1 <= 0;\r\n when 2 => Out_1 <= 1;\r\n end case C1;\r\n C2: case y is\r\n when "00" => Out_2 <= 0;\r\n when "01" => Out_2 <= 1;\r\n end case C2;\r\nend process;';
input='P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n C1: case x is\r\n when 1 => Out_1 <= 0;\r\n when 2 => Out_1 <= 1;\r\n end case C1;\r\n C2: case y is\r\n when "00" => Out_2 <= 0;\r\n when "01" => Out_2 <= 1;\r\n end case C2;\r\nend process;';
expected='P1 : PROCESS\r\n VARIABLE x : INTEGER RANGE 1 TO 3;\r\n VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n C1 : CASE x IS\r\n WHEN 1 => Out_1 <= 0;\r\n WHEN 2 => Out_1 <= 1;\r\n END CASE C1;\r\n C2 : CASE y IS\r\n WHEN "00" => Out_2 <= 0;\r\n WHEN "01" => Out_2 <= 1;\r\n END CASE C2;\r\nEND PROCESS;';
expected='P1 : PROCESS\r\n VARIABLE x : INTEGER RANGE 1 TO 3;\r\n VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n C1 : CASE x IS\r\n WHEN 1 => Out_1 <= 0;\r\n WHEN 2 => Out_1 <= 1;\r\n END CASE C1;\r\n C2 : CASE y IS\r\n WHEN "00" => Out_2 <= 0;\r\n WHEN "01" => Out_2 <= 1;\r\n END CASE C2;\r\nEND PROCESS;';
input="case READ_CPU_STATE is\r\n when WAITING =>\r\n if CPU_DATA_VALID = '1' then\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n end if;\r\n when DATA1 =>\r\n -- etc.\r\nend case;";
input="case READ_CPU_STATE is\r\n when WAITING =>\r\n if CPU_DATA_VALID = '1' then\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n end if;\r\n when DATA1 =>\r\n -- etc.\r\nend case;";
expected="CASE READ_CPU_STATE IS\r\n WHEN WAITING => \r\n IF CPU_DATA_VALID = '1' THEN\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n END IF;\r\n WHEN DATA1 => \r\n -- etc.\r\nEND CASE;";
expected="CASE READ_CPU_STATE IS\r\n WHEN WAITING => \r\n IF CPU_DATA_VALID = '1' THEN\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n END IF;\r\n WHEN DATA1 => \r\n -- etc.\r\nEND CASE;";
actual=VHDLFormatter_1.beautify(input,settings);
actual=VHDLFormatter_1.beautify(input,settings);
console.log("WHEN CASE & IF",CompareString(actual,expected));
assert("WHEN CASE & IF",expected,actual);
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\n D : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\n D : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\n D : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\n D : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
actual=VHDLFormatter_1.beautify(input,settings);
actual=VHDLFormatter_1.beautify(input,settings);
console.log("Multiple PORT MAPs",CompareString(actual,expected));
assert("Multiple PORT MAPs",expected,actual);
input="port (a : in std_logic;\r\n b : in std_logic;\r\n);";
input="port (a : in std_logic;\r\n b : in std_logic;\r\n);";
expected="PORT \r\n(\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n);";
expected="PORT \r\n(\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n);";
console.log("Align parameters in PROCESS",CompareString(actual,expected));
assert("Align parameters in PROCESS",expected,actual);
input="architecture a of b is\r\nbegin\r\n process (w)\r\n variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n a := (others => '0') ;\r\nend process ;\r\nend a;";
input="architecture a of b is\r\nbegin\r\n process (w)\r\n variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n a := (others => '0') ;\r\nend process ;\r\nend a;";
expected="ARCHITECTURE a OF b IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n BEGIN\r\n a := (OTHERS => '0');\r\n END PROCESS;\r\nEND a;";
expected="ARCHITECTURE a OF b IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n BEGIN\r\n a := (OTHERS => '0');\r\n END PROCESS;\r\nEND a;";
input="entity a is\r\n port ( w : in std_logic_vector (7 downto 0) ;\r\n w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n process ( w )\r\n variable t : std_logic_vector (4 downto 0) ;\r\n variable bcd : std_logic_vector (11 downto 0) ;\r\nbegin\r\n b(2 downto 0) := w(7 downto 5) ;\r\n t := w(4 downto 0) ;\r\n w_s <= b(11 downto 8) ;\r\n w <= b(3 downto 0) ;\r\nend process ;\r\nend b ;";
input="entity a is\r\n port ( w : in std_logic_vector (7 downto 0) ;\r\n w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n process ( w )\r\n variable t : std_logic_vector (4 downto 0) ;\r\n variable bcd : std_logic_vector (11 downto 0) ;\r\nbegin\r\n b(2 downto 0) := w(7 downto 5) ;\r\n t := w(4 downto 0) ;\r\n w_s <= b(11 downto 8) ;\r\n w <= b(3 downto 0) ;\r\nend process ;\r\nend b ;";
expected="ENTITY a IS\r\n PORT \r\n (\r\n w : IN std_logic_vector (7 DOWNTO 0);\r\n w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n BEGIN\r\n b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n t := w(4 DOWNTO 0);\r\n w_s <= b(11 DOWNTO 8);\r\n w <= b(3 DOWNTO 0);\r\n END PROCESS;\r\nEND b;";
expected="ENTITY a IS\r\n PORT \r\n (\r\n w : IN std_logic_vector (7 DOWNTO 0);\r\n w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n BEGIN\r\n b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n t := w(4 DOWNTO 0);\r\n w_s <= b(11 DOWNTO 8);\r\n w <= b(3 DOWNTO 0);\r\n END PROCESS;\r\nEND b;";
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letinput="architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;"
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
letexpected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
expected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT \r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
expected="ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT \r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
input="entity TB_DISPLAY is\r\n-- port declarations\r\nend TB_DISPLAY;\r\n\r\narchitecture TEST of TB_DISPLAY is\r\n-- signal declarations\r\nbegin\r\n-- component instance(s)\r\nend TEST;";
input="entity TB_DISPLAY is\r\n-- port declarations\r\nend TB_DISPLAY;\r\n\r\narchitecture TEST of TB_DISPLAY is\r\n-- signal declarations\r\nbegin\r\n-- component instance(s)\r\nend TEST;";
expected="ENTITY TB_DISPLAY IS\r\n -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n -- signal declarations\r\nBEGIN\r\n -- component instance(s)\r\nEND TEST;";
expected="ENTITY TB_DISPLAY IS\r\n -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n -- signal declarations\r\nBEGIN\r\n -- component instance(s)\r\nEND TEST;";
console.log("IF ELSE END IF case 2",actual==expected);
assert("IF ELSE END IF case 2",expected,actual);
input='P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n C1: case x is\r\n when 1 => Out_1 <= 0;\r\n when 2 => Out_1 <= 1;\r\n end case C1;\r\n C2: case y is\r\n when "00" => Out_2 <= 0;\r\n when "01" => Out_2 <= 1;\r\n end case C2;\r\nend process;';
input='P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n C1: case x is\r\n when 1 => Out_1 <= 0;\r\n when 2 => Out_1 <= 1;\r\n end case C1;\r\n C2: case y is\r\n when "00" => Out_2 <= 0;\r\n when "01" => Out_2 <= 1;\r\n end case C2;\r\nend process;';
expected='P1 : PROCESS\r\n VARIABLE x : INTEGER RANGE 1 TO 3;\r\n VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n C1 : CASE x IS\r\n WHEN 1 => Out_1 <= 0;\r\n WHEN 2 => Out_1 <= 1;\r\n END CASE C1;\r\n C2 : CASE y IS\r\n WHEN "00" => Out_2 <= 0;\r\n WHEN "01" => Out_2 <= 1;\r\n END CASE C2;\r\nEND PROCESS;';
expected='P1 : PROCESS\r\n VARIABLE x : INTEGER RANGE 1 TO 3;\r\n VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n C1 : CASE x IS\r\n WHEN 1 => Out_1 <= 0;\r\n WHEN 2 => Out_1 <= 1;\r\n END CASE C1;\r\n C2 : CASE y IS\r\n WHEN "00" => Out_2 <= 0;\r\n WHEN "01" => Out_2 <= 1;\r\n END CASE C2;\r\nEND PROCESS;';
input="case READ_CPU_STATE is\r\n when WAITING =>\r\n if CPU_DATA_VALID = '1' then\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n end if;\r\n when DATA1 =>\r\n -- etc.\r\nend case;";
input="case READ_CPU_STATE is\r\n when WAITING =>\r\n if CPU_DATA_VALID = '1' then\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n end if;\r\n when DATA1 =>\r\n -- etc.\r\nend case;";
expected="CASE READ_CPU_STATE IS\r\n WHEN WAITING => \r\n IF CPU_DATA_VALID = '1' THEN\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n END IF;\r\n WHEN DATA1 => \r\n -- etc.\r\nEND CASE;";
expected="CASE READ_CPU_STATE IS\r\n WHEN WAITING => \r\n IF CPU_DATA_VALID = '1' THEN\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n END IF;\r\n WHEN DATA1 => \r\n -- etc.\r\nEND CASE;";
actual=beautify(input,settings);
actual=beautify(input,settings);
console.log("WHEN CASE & IF",CompareString(actual,expected));
assert("WHEN CASE & IF",expected,actual);
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\n D : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
input="entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\n D : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\n D : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
expected="ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\n D : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
actual=beautify(input,settings);
actual=beautify(input,settings);
console.log("Multiple PORT MAPs",CompareString(actual,expected));
assert("Multiple PORT MAPs",expected,actual);
input="port (a : in std_logic;\r\n b : in std_logic;\r\n);";
input="port (a : in std_logic;\r\n b : in std_logic;\r\n);";
expected="PORT \r\n(\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n);";
expected="PORT \r\n(\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n);";
expected="PROCESS xyx (vf, fr, \r\n de -- comment\r\n )";
expected="PROCESS xyx (vf, fr, \r\n de -- comment\r\n )";
actual=beautify(input,newSettings);
actual=beautify(input,newSettings);
console.log("Align parameters in PROCESS",CompareString(actual,expected));
assert("Align parameters in PROCESS",expected,actual);
input="architecture a of b is\r\nbegin\r\n process (w)\r\n variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n a := (others => '0') ;\r\nend process ;\r\nend a;";
input="architecture a of b is\r\nbegin\r\n process (w)\r\n variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n a := (others => '0') ;\r\nend process ;\r\nend a;";
expected="ARCHITECTURE a OF b IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n BEGIN\r\n a := (OTHERS => '0');\r\n END PROCESS;\r\nEND a;";
expected="ARCHITECTURE a OF b IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n BEGIN\r\n a := (OTHERS => '0');\r\n END PROCESS;\r\nEND a;";
input="entity a is\r\n port ( w : in std_logic_vector (7 downto 0) ;\r\n w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n process ( w )\r\n variable t : std_logic_vector (4 downto 0) ;\r\n variable bcd : std_logic_vector (11 downto 0) ;\r\nbegin\r\n b(2 downto 0) := w(7 downto 5) ;\r\n t := w(4 downto 0) ;\r\n w_s <= b(11 downto 8) ;\r\n w <= b(3 downto 0) ;\r\nend process ;\r\nend b ;";
input="entity a is\r\n port ( w : in std_logic_vector (7 downto 0) ;\r\n w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n process ( w )\r\n variable t : std_logic_vector (4 downto 0) ;\r\n variable bcd : std_logic_vector (11 downto 0) ;\r\nbegin\r\n b(2 downto 0) := w(7 downto 5) ;\r\n t := w(4 downto 0) ;\r\n w_s <= b(11 downto 8) ;\r\n w <= b(3 downto 0) ;\r\nend process ;\r\nend b ;";
expected="ENTITY a IS\r\n PORT \r\n (\r\n w : IN std_logic_vector (7 DOWNTO 0);\r\n w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n BEGIN\r\n b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n t := w(4 DOWNTO 0);\r\n w_s <= b(11 DOWNTO 8);\r\n w <= b(3 DOWNTO 0);\r\n END PROCESS;\r\nEND b;";
expected="ENTITY a IS\r\n PORT \r\n (\r\n w : IN std_logic_vector (7 DOWNTO 0);\r\n w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n BEGIN\r\n b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n t := w(4 DOWNTO 0);\r\n w_s <= b(11 DOWNTO 8);\r\n w <= b(3 DOWNTO 0);\r\n END PROCESS;\r\nEND b;";
actual=beautify(input,newSettings2);
actual=beautify(input,newSettings2);
console.log("Align signs in all places",CompareString(actual,expected));
assert("Align signs in all places",expected,actual);
input="begin\r\n P0 : process(input)\r\n variable value: Integer;\r\n begin\r\n result(i) := '0';\r\n end process P0;\r\nend behavior;";
input="begin\r\n P0 : process(input)\r\n variable value: Integer;\r\n begin\r\n result(i) := '0';\r\n end process P0;\r\nend behavior;";
expected="BEGIN\r\n P0 : PROCESS (input)\r\n VARIABLE value : INTEGER;\r\n BEGIN\r\n result(i) := '0';\r\n END PROCESS P0;\r\nEND behavior;";
expected="BEGIN\r\n P0 : PROCESS (input)\r\n VARIABLE value : INTEGER;\r\n BEGIN\r\n result(i) := '0';\r\n END PROCESS P0;\r\nEND behavior;";
actual=beautify(input,newSettings);
actual=beautify(input,newSettings);
console.log("Indent after Begin",CompareString(actual,expected));