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238 lines
16 KiB
238 lines
16 KiB
"use strict";
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Object.defineProperty(exports, "__esModule", { value: true });
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const VHDLFormatter_1 = require("./VHDLFormatter");
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const VHDLFormatter_2 = require("./VHDLFormatter");
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const VHDLFormatter_3 = require("./VHDLFormatter");
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const VHDLFormatter_4 = require("./VHDLFormatter");
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const VHDLFormatter_5 = require("./VHDLFormatter");
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const VHDLFormatter_6 = require("./VHDLFormatter");
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const VHDLFormatter_7 = require("./VHDLFormatter");
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let testCount = 0;
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var showUnitTests = true; //window.location.href.indexOf("http") < 0;
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if (showUnitTests) {
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testCount = 0;
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UnitTest();
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UnitTestIndentDecode();
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UnitTestRemoveAsserts();
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UnitTestApplyNoNewLineAfter();
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UnitTestSetNewLinesAfterSymbols();
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console.log("total tests: " + testCount);
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}
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function UnitTestSetNewLinesAfterSymbols() {
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console.log("=== SetNewLinesAfterSymbols ===");
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let input = "a; @@comments1\r\nb;";
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let expected = "a; @@comments1\r\nb;";
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let parameters = new VHDLFormatter_3.NewLineSettings();
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parameters.newLineAfter = ["then", ";"];
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parameters.noNewLineAfter = ["port", "generic"];
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UnitTest5(VHDLFormatter_7.SetNewLinesAfterSymbols, "no new line after comment", parameters, input, expected);
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input = "a; b;";
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expected = "a;\r\nb;";
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UnitTest5(VHDLFormatter_7.SetNewLinesAfterSymbols, "new line after ;", parameters, input, expected);
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}
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function UnitTestApplyNoNewLineAfter() {
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console.log("=== ApplyNoNewLineAfter ===");
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let input = ["a;", "b;"];
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let expected = ["a;@@singleline", "b;@@singleline"];
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let parameters = [";"];
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UnitTest4(VHDLFormatter_6.ApplyNoNewLineAfter, "one blankspace", parameters, input, expected);
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input = ["a;", "b THEN", "c"];
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expected = ["a;@@singleline", "b THEN@@singleline", "c"];
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parameters = [";", "then"];
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UnitTest4(VHDLFormatter_6.ApplyNoNewLineAfter, "one blankspace", parameters, input, expected);
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}
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function UnitTestRemoveAsserts() {
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console.log("=== RemoveAsserts ===");
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let input = ["ASSERT a;"];
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let expected = [""];
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UnitTest3(VHDLFormatter_5.RemoveAsserts, "one assert", input, expected);
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input = ["ASSERT a", "b;", "c"];
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expected = ["", "", "c"];
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UnitTest3(VHDLFormatter_5.RemoveAsserts, "multiline assert", input, expected);
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}
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function UnitTestIndentDecode() {
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console.log("=== IndentDecode ===");
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UnitTest2(VHDLFormatter_2.indentDecode, "one blankspace", " ", "one blankspace");
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UnitTest2(VHDLFormatter_2.indentDecode, "mixed chars", " A ", "one blankspace & one A & one blankspace");
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UnitTest2(VHDLFormatter_2.indentDecode, "4 blankspaces", " ", "four blankspace");
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UnitTest2(VHDLFormatter_2.indentDecode, "9 blankspaces", " ", "many blankspace");
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}
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function assert(testName, expected, actual, message) {
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var result = CompareString(actual, expected);
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if (result != true) {
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console.log(testName + " failed: " + result);
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}
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else {
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//console.log(testName + " pass");
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}
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testCount++;
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}
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function assertArray(testName, expected, actual, message) {
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var result = CompareArray(actual, expected);
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if (result != true) {
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console.log(testName + " failed: " + result);
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}
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else {
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//console.log(testName + " pass");
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}
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testCount++;
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}
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function UnitTest5(func, testName, parameters, inputs, expected) {
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let actual = func(inputs, parameters);
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assert(testName, expected, actual);
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}
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function UnitTest4(func, testName, parameters, inputs, expected) {
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let actual = JSON.parse(JSON.stringify(inputs));
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func(actual, parameters);
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assertArray(testName, expected, actual);
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}
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function UnitTest3(func, testName, inputs, expected) {
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let actual = JSON.parse(JSON.stringify(inputs));
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func(actual);
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assertArray(testName, expected, actual);
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}
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function UnitTest2(func, testName, inputs, expected) {
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let actual = func(inputs);
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assert(testName, expected, actual);
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}
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function deepCopy(objectToCopy) {
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return (JSON.parse(JSON.stringify(objectToCopy)));
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}
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function UnitTest() {
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let new_line_after_symbols = new VHDLFormatter_3.NewLineSettings();
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new_line_after_symbols.newLineAfter = ["then", ";"];
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new_line_after_symbols.noNewLineAfter = ["port", "generic"];
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let settings = new VHDLFormatter_4.BeautifierSettings(false, false, false, false, false, "uppercase", " ", new_line_after_symbols);
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let input = "architecture TB of TB_CPU is\r\n component CPU_IF\r\n port -- port list\r\n end component;\r\n signal CPU_DATA_VALID: std_ulogic;\r\n signal CLK, RESET: std_ulogic := '0';\r\n constant PERIOD : time := 10 ns;\r\n constant MAX_SIM: time := 50 * PERIOD;\r\n begin\r\n -- concurrent statements\r\n end TB;";
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let expected = "ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT -- port list\r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\n -- concurrent statements\r\nEND TB;";
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let actual = VHDLFormatter_1.beautify(input, settings);
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assert("General", expected, actual);
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let newSettings = deepCopy(settings);
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newSettings.RemoveComments = true;
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expected = "ARCHITECTURE TB OF TB_CPU IS\r\n COMPONENT CPU_IF\r\n PORT \r\n END COMPONENT;\r\n SIGNAL CPU_DATA_VALID : std_ulogic;\r\n SIGNAL CLK, RESET : std_ulogic := '0';\r\n CONSTANT PERIOD : TIME := 10 ns;\r\n CONSTANT MAX_SIM : TIME := 50 * PERIOD;\r\nBEGIN\r\nEND TB;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Remove comments", expected, actual);
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let new_line_after_symbols_2 = new VHDLFormatter_3.NewLineSettings();
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new_line_after_symbols_2.newLineAfter = [];
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new_line_after_symbols_2.noNewLineAfter = ["then", ";", "generic", "port"];
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newSettings = deepCopy(settings);
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newSettings.NewLineSettings = new_line_after_symbols_2;
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expected = "a; b; c;";
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input = "a; \r\nb;\r\n c;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Remove line after ;", expected, actual);
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newSettings = deepCopy(settings);
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newSettings.RemoveAsserts = true;
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input = "architecture arch of ent is\r\nbegin\r\n assert False report sdfjcsdfcsdj;\r\n assert False report sdfjcsdfcsdj severity note;\r\nend architecture;";
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expected = "ARCHITECTURE arch OF ent IS\r\nBEGIN\r\nEND ARCHITECTURE;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Remove asserts", expected, actual);
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input = "entity TB_DISPLAY is\r\n-- port declarations\r\nend TB_DISPLAY;\r\n\r\narchitecture TEST of TB_DISPLAY is\r\n-- signal declarations\r\nbegin\r\n-- component instance(s)\r\nend TEST;";
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expected = "ENTITY TB_DISPLAY IS\r\n -- port declarations\r\nEND TB_DISPLAY;\r\n\r\nARCHITECTURE TEST OF TB_DISPLAY IS\r\n -- signal declarations\r\nBEGIN\r\n -- component instance(s)\r\nEND TEST;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("ENTITY ARCHITECTURE", expected, actual);
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newSettings = deepCopy(settings);
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newSettings.SignAlign = true;
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input = "port map(\r\ninput_1 => input_1_sig,\r\ninput_2 => input_2_sig,\r\noutput => output_sig\r\n);";
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expected = "PORT MAP(\r\n input_1 => input_1_sig, \r\n input_2 => input_2_sig, \r\n output => output_sig\r\n);";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Sign align in PORT", expected, actual);
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input = 'if a(3 downto 0) > "0100" then\r\na(3 downto 0) := a(3 downto 0) + "0011" ;\r\nend if ;';
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expected = 'IF a(3 DOWNTO 0) > "0100" THEN\r\n a(3 DOWNTO 0) := a(3 DOWNTO 0) + "0011";\r\nEND IF;';
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("IF END IF case 1", expected, actual);
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input = "if s = '1' then\r\no <= \"010\";\r\nelse\r\no <= \"101\";\r\nend if;";
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expected = "IF s = '1' THEN\r\n o <= \"010\";\r\nELSE\r\n o <= \"101\";\r\nEND IF;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("IF ELSE END IF case 1", expected, actual);
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input = "IF (s = r) THEN rr := '0'; ELSE rr := '1'; END IF;";
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expected = "IF (s = r) THEN\r\n rr := '0';\r\nELSE\r\n rr := '1';\r\nEND IF;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("IF ELSE END IF case 2", expected, actual);
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input = 'P1:process\r\nvariable x: Integer range 1 to 3;\r\nvariable y: BIT_VECTOR (0 to 1);\r\nbegin\r\n C1: case x is\r\n when 1 => Out_1 <= 0;\r\n when 2 => Out_1 <= 1;\r\n end case C1;\r\n C2: case y is\r\n when "00" => Out_2 <= 0;\r\n when "01" => Out_2 <= 1;\r\n end case C2;\r\nend process;';
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expected = 'P1 : PROCESS\r\n VARIABLE x : INTEGER RANGE 1 TO 3;\r\n VARIABLE y : BIT_VECTOR (0 TO 1);\r\nBEGIN\r\n C1 : CASE x IS\r\n WHEN 1 => Out_1 <= 0;\r\n WHEN 2 => Out_1 <= 1;\r\n END CASE C1;\r\n C2 : CASE y IS\r\n WHEN "00" => Out_2 <= 0;\r\n WHEN "01" => Out_2 <= 1;\r\n END CASE C2;\r\nEND PROCESS;';
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("WHEN CASE", expected, actual);
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input = "case READ_CPU_STATE is\r\n when WAITING =>\r\n if CPU_DATA_VALID = '1' then\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n end if;\r\n when DATA1 =>\r\n -- etc.\r\nend case;";
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expected = "CASE READ_CPU_STATE IS\r\n WHEN WAITING => \r\n IF CPU_DATA_VALID = '1' THEN\r\n CPU_DATA_READ <= '1';\r\n READ_CPU_STATE <= DATA1;\r\n END IF;\r\n WHEN DATA1 => \r\n -- etc.\r\nEND CASE;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("WHEN CASE & IF", expected, actual);
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input = "entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
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expected = "ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("PORT MAP", expected, actual);
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input = "entity aa is\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port (a : in std_logic;\r\n b : in std_logic;\r\n );\r\nend aa;\r\narchitecture bb of aa is\r\n component cc\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n port(\r\n a : in std_logic;\r\n b : in std_logic;\r\n );\r\n end cc;\r\n\r\nbegin\r\n C : cc port map (\r\n long => a,\r\n b => b\r\n );\r\n D : cc port map (\r\n long => a,\r\n b => b\r\n );\r\nend;";
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expected = "ENTITY aa IS\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\nEND aa;\r\nARCHITECTURE bb OF aa IS\r\n COMPONENT cc\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n PORT (\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n );\r\n END cc;\r\n\r\nBEGIN\r\n C : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\n D : cc\r\n PORT MAP(\r\n long => a, \r\n b => b\r\n );\r\nEND;";
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actual = VHDLFormatter_1.beautify(input, settings);
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assert("Multiple PORT MAPs", expected, actual);
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input = "port (a : in std_logic;\r\n b : in std_logic;\r\n);";
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expected = "PORT \r\n(\r\n a : IN std_logic;\r\n b : IN std_logic;\r\n);";
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new_line_after_symbols_2 = new VHDLFormatter_3.NewLineSettings();
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new_line_after_symbols_2.newLineAfter = ["then", ";", "generic", "port"];
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newSettings = deepCopy(settings);
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newSettings.NewLineSettings = new_line_after_symbols_2;
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("New line after PORT", expected, actual);
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input = "component a is\r\nport( Data : inout Std_Logic_Vector(7 downto 0););\r\nend component a;";
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expected = "COMPONENT a IS\r\n PORT (Data : INOUT Std_Logic_Vector(7 DOWNTO 0););\r\nEND COMPONENT a;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("New line aster PORT (single line)", expected, actual);
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input = "process xyx (vf,fr,\r\nde -- comment\r\n)";
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expected = "PROCESS xyx (vf, fr, \r\n de -- comment\r\n )";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Align parameters in PROCESS", expected, actual);
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input = "architecture a of b is\r\nbegin\r\n process (w)\r\n variable t : std_logic_vector (4 downto 0) ;\r\nbegin\r\n a := (others => '0') ;\r\nend process ;\r\nend a;";
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expected = "ARCHITECTURE a OF b IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n BEGIN\r\n a := (OTHERS => '0');\r\n END PROCESS;\r\nEND a;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Double BEGIN", expected, actual);
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let newSettings2 = deepCopy(newSettings);
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newSettings2.SignAlignAll = true;
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input = "entity a is\r\n port ( w : in std_logic_vector (7 downto 0) ;\r\n w_s : out std_logic_vector (3 downto 0) ; ) ;\r\nend a ;\r\narchitecture b of a is\r\nbegin\r\n process ( w )\r\n variable t : std_logic_vector (4 downto 0) ;\r\n variable bcd : std_logic_vector (11 downto 0) ;\r\nbegin\r\n b(2 downto 0) := w(7 downto 5) ;\r\n t := w(4 downto 0) ;\r\n w_s <= b(11 downto 8) ;\r\n w <= b(3 downto 0) ;\r\nend process ;\r\nend b ;";
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expected = "ENTITY a IS\r\n PORT \r\n (\r\n w : IN std_logic_vector (7 DOWNTO 0);\r\n w_s : OUT std_logic_vector (3 DOWNTO 0); \r\n );\r\nEND a;\r\nARCHITECTURE b OF a IS\r\nBEGIN\r\n PROCESS (w)\r\n VARIABLE t : std_logic_vector (4 DOWNTO 0);\r\n VARIABLE bcd : std_logic_vector (11 DOWNTO 0);\r\n BEGIN\r\n b(2 DOWNTO 0) := w(7 DOWNTO 5);\r\n t := w(4 DOWNTO 0);\r\n w_s <= b(11 DOWNTO 8);\r\n w <= b(3 DOWNTO 0);\r\n END PROCESS;\r\nEND b;";
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actual = VHDLFormatter_1.beautify(input, newSettings2);
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assert("Align signs in all places", expected, actual);
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input = "begin\r\n P0 : process(input)\r\n variable value: Integer;\r\n begin\r\n result(i) := '0';\r\n end process P0;\r\nend behavior;";
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expected = "BEGIN\r\n P0 : PROCESS (input)\r\n VARIABLE value : INTEGER;\r\n BEGIN\r\n result(i) := '0';\r\n END PROCESS P0;\r\nEND behavior;";
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actual = VHDLFormatter_1.beautify(input, newSettings);
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assert("Indent after Begin", expected, actual);
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}
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function CompareString(actual, expected) {
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var l = Math.min(actual.length, expected.length);
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for (var i = 0; i < l; i++) {
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if (actual[i] != expected[i]) {
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var toEnd = Math.min(i + 50, l);
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return '\ndifferent at ' + i.toString() +
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'\nactual: "\n' + actual.substring(i, toEnd) +
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'\nexpected: "\n' + expected.substring(i, toEnd) + '"\n---' +
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"\nactual (full): \n" + actual + "\n---" +
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"\nexpected (full): \n" + expected + "\n====\n";
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}
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}
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if (actual != expected) {
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return 'actual: \n"' + actual + '"\nexpected: \n"' + expected + '"';
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}
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return true;
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}
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function CompareArray(actual, expected) {
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var l = Math.min(actual.length, expected.length);
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let result = "";
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for (var i = 0; i < l; i++) {
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if (actual[i] != expected[i]) {
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result += CompareString(actual[i], expected[i]) + "\n";
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}
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}
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if (actual.length > expected.length) {
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result += "actual has more items";
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for (var i = expected.length; i < actual.length; i++) {
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result += "actual[" + i + "] = " + actual[i];
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}
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}
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else if (actual.length < expected.length) {
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result += "expected has more items";
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for (var i = actual.length; i < expected.length; i++) {
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result += "expected[" + i + "] = " + expected[i];
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}
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}
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return true;
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}
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//# sourceMappingURL=VHDLFormatterUnitTests.js.map
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