indent multi-line signal and constant declarations

for example:
signal test_sig : type_sig := (
    a => '0', -- now correctly indented
    b => '0'
);

VHDLFormatter.js

@@ -635,6 +635,10 @@ function beautify3(inputs, result, settings, startIndex, indent, endIndex) {
             [i, endIndex] = beautifyPortGenericBlock(inputs, result, settings, i, endIndex, indent, "GENERIC");
             continue;
         }
+        if (input.regexStartsWith(/.*?\:\=\s*\($/)) {
+            [i, endIndex] = beautifyPortGenericBlock(inputs, result, settings, i, endIndex, indent, ":=");
+            continue;
+        }
         if (input.regexStartsWith(/[\w\s:]*PROCEDURE[\s\w]+\($/)) {
             [i, endIndex] = beautifyPortGenericBlock(inputs, result, settings, i, endIndex, indent, "PROCEDURE");
             if (inputs[i].regexStartsWith(/.*\)[\s]*IS/)) {
@@ -760,4 +764,4 @@ function RemoveExtraNewLines(input) {
     input = input.replace(/\r\n\r\n\r\n/g, '\r\n');
     return input;
 }
-//# sourceMappingURL=VHDLFormatter.js.map
+//# sourceMappingURL=VHDLFormatter.js.map

VHDLFormatter.ts

@@ -694,6 +694,10 @@ export function beautify3(inputs: Array<string>, result: (FormattedLine | Format
             Mode = modeCache;
             continue;
         }
+        if (input.regexStartsWith(/.*?\:\=\s*\($/)) {
+            [i, endIndex] = beautifyPortGenericBlock(inputs, result, settings, i, endIndex, indent, ":=");
+            continue;
+        }
         if (input.regexStartsWith(/[\w\s:]*\bPORT\b([\s]|$)/)) {
             [i, endIndex] = beautifyPortGenericBlock(inputs, result, settings, i, endIndex, indent, "PORT");
             continue;